Switched capacitor integrator using unity gain buffers

Details Switched capacitor integrator using unity gain buffers Switched capacitor integrator using unity gain buffers

2000-11-17

2002-06-11

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

By integrating

C327S095000, C327S094000, C327S554000

Reexamination Certificate

active

06404262

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic devices and more particularly to a switched capacitor integrator using unity gain buffers.
BACKGROUND OF THE INVENTION
Switched-capacitor (S-C) analog sampled-data techniques are widely used in CMOS integrated filters, analog-to-digital and digital-to-analog converters. The use of a capacitor in series with a switch to sample a voltage and accumulate charge to perform integration is rudimentary to this technology.
FIGS. 1
a
-
1
c
show examples of a switched capacitor, with
FIG. 1
a
illustrating a switched capacitor
10
with one switch
12
and
FIG. 1
b
showing the same circuit with two switches
14
. and
16
.
FIG. 1
c
illustrates a MOS (metal oxide semiconductor) implementation of the switches
14
and
16
. Typically MOS switches
14
and
16
are controlled by two-phase, non-overlapping clocks. For example, one clock signal would be applied to the gate (control terminal) of transistor
14
while a second non-overlapping clock signal is applied to the gate of transistor
16
.
The influence of parasitic capacitors in switched capacitor circuits is minimized using operational-amplifiers (opamps). There are well-known circuit topologies for performing amplification and integration. For example,
FIG. 2
a
illustrates a switched capacitor integrator and
FIG. 2
b
illustrates a timing diagram for a two-phase clock that can be utilized with the circuit of
FIG. 2
a
. In this circuit, opamp
18
is provided with a first input coupled to switch
22
while the second input is grounded. Capacitor
24
is coupled between switch
20
and switch
22
. Switches
26
and
28
are also provided to reset the capacitor before applying input voltage V
in
. Capacitor
20
is coupled between the first (negative) input and the output of opamp
18
.
During the first phase of the clock, switches
26
and
28
are closed so that both plates of the capacitor are grounded (or discharged). Alternatively, other voltages besides ground could be used. During the second phase of the clock, switches
26
and
28
are opened and switches
20
and
24
are closed. This causes the input voltage V
in
be transfer across capacitor
24
and be added to the output voltage at node V
out
. Operational amplifier realization, however, becomes very difficult as circuit design moves up in the frequency domain.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides an alternative to the use of operational amplifiers in switched capacitor applications. For example, the preferred embodiment of the present invention utilizes unity gain buffers to implement a switched capacitor integrator. It is relatively easier to achieve unity-gain buffers such as source followers at high frequencies.
In the preferred embodiment, the present invention presents a circuit that employs unity-gain buffers instead of operational amplifiers to perform integration of an input signal. This is achieved by adding sampled values of input voltage in series to obtain the sum. Both recursive and non-recursive integrator architectures are presented. Assuming unity-gain for the buffer, the operation of integration is accurate. While the influence of linear parasitic capacitance in the circuit introduces a gain-factor (e.g., &agr;<1), this does not cause a major problem in many applications like sigma-delta converters.
As an example, an electronic circuit of the present would include first and second buffers, preferably unity gain buffers. A first switch (e.g., a NMOS transistor or a CMOS transmission gate) is coupled between the output of the first buffer and the first terminal of a capacitor. This input of the second buffer is also coupled to the first terminal of the capacitor. A second switch is coupled between the second terminal of the capacitor and a first voltage node and a third switch is coupled between the second terminal of the capacitor and a second voltage node. This circuit can be used as an integrator in a number of applications.
The present invention has a number of advantages over prior art implementations, especially those that use operational amplifiers. For example, the preferred circuit implementations are well suited form low power applications. For example, the source follower configuration of a unity gain buffer provides a lower power implementation than operational amplifiers. These circuits will also be able to operate at higher frequencies.
In addition, unity gain buffers are easier to design than operational amplifiers. This fact will become especially significant as operational voltages drop to 1.5 volts to 1 volt and lower. Under these circumstances, the type of circuitry necessary to implement the present invention is easier to design than an operational amplifier.


REFERENCES:
patent: 4156923 (1979-05-01), Lampe et al.
patent: 4752741 (1988-06-01), Kim et al.
patent: 5699006 (1997-12-01), Zele et al.
patent: 5920209 (1999-07-01), Kusumoto et al.
patent: 6064239 (2000-05-01), Matsuoka
patent: 6069500 (2000-05-01), Kao
M.S. Ghausi, “Electronic Device and Circuits: Discrete and Integrated” University of California at Davis, pp. 405-408, 429-435, 1985.

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