Switched-capacitor integrator

Details Switched-capacitor integrator Switched-capacitor integrator

2002-06-26

2004-10-12

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

By integrating

C327S344000, C327S345000

Reexamination Certificate

active

06803802

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a switched-capacitor integrator and, more particularly, to a switched-capacitor integrator for eliminating switching noise.
DESCRIPTION OF RELATED ART
FIG. 1A
shows a circuit diagram of a typical integrator which is a basic filter circuit in an electronic circuit implementing filters. The integrator includes an operational amplifier A for amplifying voltage passing through its negative input node and for outputting an output voltage signal V
out
(t), a feedback capacitor C
2
connecting the negative input node and an output node of the operational amplifier A and a resistor R
1
connecting a voltage input node of V
in
(t) and the negative input node of the operational amplifier A. The transfer function and frequency characteristics of the integrator are H(s)=−1/R
1
C
2
*1/s.
When embodying the integrator of
FIG. 1A
in an integrated circuit, the resistor and capacitor of the integrator have accuracy errors of approximately 5% and 1%, respectively. These errors vary substantially with the operation environment, such as manufacturing process, temperature and use time, making it difficult to obtain accurate and reliable frequency characteristics. Therefore, in order to solve the above problem of the integrated circuit, there has been introduced a switched-capacitor circuit illustrated in FIG.
1
B.
The switched-capacitor circuit will be explained with reference to FIG.
1
B.
First of all, &phgr;
1
and &phgr;
2
are non-overlapping two-phase clock signals and a charge of Q
1
=C
1
*V
1
is stored in C
1
while &phgr;
1
has a ‘1’ state. After one half period of the two-phase clock signals &phgr;
1
and &phgr;
2
, wherein &phgr;
2
has a ‘1’ state, C
1
is coupled with V
2
and, thus, a charge of Q
2
=C
1
*V
2
is stored in C
1
. At this time, a charge of &Dgr;Q=C
1
(V
1
-V
2
) flows from the switched-capacitor C
1
. Therefore, during the one clock period T, an average current of I=&Dgr;Q/T=C
1
(V
1
-V
2
)/T, which can be represented as (V
1
-V
2
)/R
eq
, flows from V
1
to V
2
. Accordingly, the switched-capacitor circuit can be implemented by using an equivalent resistor R
eq
.
The switched-capacitor circuit can be readily integrated on a single chip through the use of a CMOS manufacturing process and has advantages of removing resistors and reducing power consumption. As a result, it can be used in almost any analog integrated filter. Further, a filter using the switched-capacitor circuit expresses the frequency characteristics of the integrator as a capacitance ratio and, therefore, it can provide high accuracy and operational reliability.
Referring to
FIG. 1C
, there is provided an integration circuit using a switched-capacitor.
The switched-capacitor integrator includes an operational amplifier A, a capacitor C
2
connected between a negative input node and an output node of the operational amplifier A, two switches S
1
and S
2
and a capacitor C
1
connected between a connection node of the two switches S
1
and S
2
and a ground voltage node. The switches S
1
and S
2
alternately perform a switching operation in response to the non-overlapping two-phase clock signals &phgr;
1
and &phgr;
2
as described above.
When forming a capacitor on a practical integrated circuit, parasitic capacitance occurs at both ends of the capacitor, which has an influence on the frequency characteristics of the integrator. In order to exclude this influence, both ends of the parasitic capacitance should be connected to a certain voltage, a ground voltage source or the input or output node of the operational amplifier A at any clock signal &phgr;
1
or &phgr;
2
to avoid their floating states.
FIG. 1D
illustrates a switched-capacitor integrator performing an integration operation regardless of the parasitic capacitance through the use of the above scheme.
The switched-capacitor integrator of
FIG. 1D
further includes switches S
3
and S
4
at both ends of the capacitor C
1
shown in FIG.
1
C. Switches S
3
and S
4
operate alternately in response to the non-overlapping two-phase clock signals &phgr;
1
and &phgr;
2
, respectively, like the switches S
1
and S
2
.
Herein, capacitors C
P1L
, C
P1R
, C
P2L
and C
P2R
represent parasitic capacitance caused at both ends of the capacitors C
1
and C
2
, respectively.
At first, when considering the parasitic capacitors C
P1L
and C
P1R
related to the capacitor C
1
, one end of the parasitic capacitor C
P1L
is connected to an input voltage V
in
if an actuated clock input, e.g., having a ‘1’ state, is &phgr;
1
and, thus, the switch S
1
is on. On the other hand, the other end of the parasitic capacitor C
P1L
is attached to the ground voltage source if the actuated clock input is &phgr;
2
and, thus, the switch S
4
is on. In the mean time, one end of the parasitic capacitor C
P1R
is coupled to the ground voltage source if the actuated clock input is &phgr;
1
and, thus, the switch S
3
is on. On the other hand, the other end of the parasitic capacitor C
P1R
is attached to a negative input node of the operational amplifier A if the actuated clock input is &phgr;
2
and, thus, the switch S
2
is on. As a result, both ends of the parasitic capacitor are connected to a certain voltage, such as V
in
, the ground voltage source or the input node of the operational amplifier A, at any actuated clock signal &phgr;
1
or &phgr;
2
.
Meanwhile, the parasitic capacitor C
P2L
of capacitor C
2
is always connected to a virtual ground voltage source and the parasitic capacitor C
P2R
of capacitor C
2
is attached to the output node of the operational amplifier A. Therefore, the parasitic capacitors C
P2L
and C
P2R
do not have an influence on the operation of the integrator.
Referring to
FIG. 2
, there is shown a circuit diagram of a switched-capacitor integrator including a reference voltage unit in addition to the integrator of FIG.
1
D.
The switched-capacitor integrator comprises a first and a second switch SW
1
and SW
2
providing input signals V
a
and V
b
, respectively, to one end of an input capacitor C
1
, a first operational amplifier A
1
receiving a reference voltage V
c
as its positive input and whose output node is connected with its negative input node, a third switch SW
3
connecting the output node N
2
of the first operational amplifier A
1
with the other end N
1
of the input capacitor C
1
, a second operational amplifier A
2
receiving a signal from the input capacitor C
1
through a fourth switch SW
4
as its positive input and the output of the first operational amplifier A
1
as its negative input, and a feedback capacitor C
2
connecting an output signal V
out
with the negative input of the second operational amplifier A
2
.
Hereinafter, the operation of the switched-capacitor integrator employing the reference voltage unit will be explained with reference to FIG.
2
. As described above, &phgr;
1
and &phgr;
2
are the non-overlapping two-phase clock signals. Furthermore, the first and third switches SW
1
and SW
3
operate in response to the first phase clock signal &phgr;
1
and the second and fourth switches SW
2
and SW
4
operate under the control of the second phase clock signal &phgr;
2
.
That is, if the first phase clock signal &phgr;
1
is actuated and, thus, the first and third switches SW
1
and SW
3
are on, a charge of C
1
(V
a
-V
c
) is stored in the input capacitor C
1
. On the other hand, if the second phase clock signal &phgr;
2
is actuated and, thus, the second and fourth switches SW
2
and SW
4
are on, a charge of C
1
(V
b
-V
c
) is stored in the input capacitor C
1
. Therefore, during one clock period, a charge of {C
1
(V
a
-V
c
)}−{C
1
(V
b
-V
c
)}=C
1
(V
a
-V
b
)moves from the input capacitor C
1
to the feedback capacitor C
2
according to the law of conservation of quantity of electric charge.
When the actuated clock signal changes from &phgr;
2
to &phgr;
1
, the amount of charge stored in the input capacitor C
1
cannot change suddenly from C
1
(V
b
-V
c
) to

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