Switched capacitor filter circuit having reduced offsets and...

Pulse or digital communications – Receivers – Interference or noise reduction

Reexamination Certificate

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C341S172000, C327S337000, C327S554000

Reexamination Certificate

active

06351506

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to switched capacitor filter circuits, and in particular, switched capacitor filter circuits having reduced offsets and providing offset compensation when used in closed feedback loops.
2. Description of the Related Art
Cellular telephones typically operate in a standby mode in which most active receiver circuitry is powered up, or enabled, only long enough to detect the presence of an incoming call. This so-called “power-up” time is typically in the range of 20 percent. Added to this 20 percent “power-up” time is the overhead time needed to initialize the system, e.g., the time needed to achieve phase lock within the phase lock loops of the system and to compensate for receiver circuit offsets. Hence, if the overhead time is 5 percent, then the average power dissipation during standby mode has increased by 25 percent (0.25/0.2=1.25). Accordingly, it follows that if the overhead time can be reduced then the average power dissipation during standby operation can also be reduced. For example, one conventional CDMA (code division multiple access) spread spectrum cellular system has a typical overhead time of approximately four milliseconds (ms), and it has been a goal to reduce such overhead time by a factor of four to approximately 1 ms.
Referring to
FIG. 1
, cellular telephones, as with most communication systems, require high gain baseband filters within the receive signal path. In such applications, the in-band signal is amplified and conveyed to subsequent stages for processing, e.g., to an analog-to-digital converter (ADC). This analog filtering serves two purposes: reducing the magnitude of interfering signals outside the band of interest; and providing anti-aliasing. With respect to the former purpose, reducing the magnitude of interfering signals outside of the band of interest prevents large out-of-band signals from reducing the dynamic range of the system. However, it is important that the power dissipated within the filter be less than the power that would be required for an ADC with sufficient resolution to handle such out-of-band interference. For example, if the out-of-band interference is 40 decibels (dB) higher than the in-band signals, the resolution of the ADC, without such filtering, would increase from four bits to 11 bits.
Referring to
FIG. 2
, and with respect to the latter purpose, providing anti-aliasing is achieved by causing the frequency selectivity of the filter to reduce the magnitude of signals beyond the Nyquist rate of the ADC to prevent such signals from “aliasing” back into the passband as a result of the sampling process and thereby further reducing the dynamic range.
The DC offsets in the receive signal path cause performance of the system to degrade in at least two ways. Offsets near the front end of the system get amplified by the active filter circuit and thereby reduce the available dynamic range of the ADC at the output. Additionally, referring to
FIG. 3
, offsets create errors in the two receiver signal paths commonly referred to as “in-phase” (I) and “quadrature” (Q) signal paths, thereby creating constellation distortion. The magnitude of the error E equals the difference between the ideal I and Q signal vectors. These errors decrease the available signal-to-noise (SNR) ratio, thereby further reducing the system performance. For example, in one conventional type of cellular telephone, the receiver input data is encoded using quadrature phase shift keying (QPSK). The offsets create an error vector e which causes the constellation points to shift. (The ideal constellation vectors are identified by dashed lines, while the actual resultant constellation vectors are identified with bold lines.) The magnitude of the error vector is computed according to Equation (1).
|E|=
{square root over (
VOS
I
2
+VOS
Q
2
+L )}≅2·{square root over (
VOS
MAX
+L )}  (1)
In one typical cellular telephone receiver, the four-bit ADC within the received signal path operates with a nominal peak-to-peak signal range of 12 digital counts. A maximum offset of one LSB (least significant bit) results in an error vector of 17 percent. Accordingly, in order to reduce this error to 10 percent, it is necessary that the offset be kept to less than one LSB.
Referring to
FIG. 4
, offset within the quadrature signal paths has been removed in conventional systems by using a low frequency feedback loop to cancel such offset component. In a conventional CDMA spread spectrum cellular telephone system, for example, the baseband information bandwidth extends from one to 630 kilohertz (kHz). So as to not attenuate the low frequency baseband information, the offset cancellation loop bandwidth must be kept well below 1 kHz. So as to maintain signal integrity, low frequency phase response and group delay matching between the I and Q channels is just as important as magnitude matching. The offset cancellation loop bandwidth is typically set to approximately 100 hertz (Hz) to satisfy such requirements.
This conventional design provides offset compensation feedback by way of a pulse density modulated (PDM) output signal generated by a modulator/demodulator (MODEM) chip. This digital signal is filtered by a first order resistive-capacitive (RC) network. The output of this filter is fed into the analog receive filter with a nominal gain of −50% full scale for every +1 volt change in the control voltage. In the worst of cases, the offset values for the transconductive-capacitive (gm-C) filters used in conventional systems are approximately 50% of full scale, e.g., eight counts of a four-bit ADC. As a result of this large potential initial offset error, these loops can take up to 4 ms to converge within 0.5 LSB (2.5 time constants of a 100 Hz filter).
SUMMARY OF THE INVENTION
A circuit containing an embodiment of the present invention provides an offset compensation technique for high gain switched capacitor filters, such as those providing a voltage gain of at least 30 dB, thereby reducing bit error rates caused by such offsets in digital communication systems. Chopper stabilization is used in the amplifier within the filter to reduce offsets. The signal, or tone, at the chopper signal frequency is filtered out with a switched capacitor filter having a cosine filter response. Such a combination of chopper stabilization and switched capacitor cosine filtering virtually eliminates offsets without creating extraneous frequency components in the output of the high gain filter circuit.
In accordance with one embodiment of the present invention, a switched capacitor filter circuit having reduced offsets and providing offset compensation when used in a closed feedback loop includes a signal combining circuit, a chopper stabilized amplified filter circuit, an output filter circuit and an analog-to-digital conversion (ADC) circuit. The signal combining circuit is configured to receive and combine an input data signal and an offset compensation signal and in accordance therewith provide a compensated data signal. The chopper stabilized amplified filter circuit is coupled to the signal combining circuit and is configured to receive one or more chop control signals and in accordance therewith receive and low pass filter the compensated data signal and in accordance therewith provide a low pass filtered signal with an out of band signal frequency component which is at a frequency of the one or more chop control signals and represents an offset and 1/f noise of the chopper stabilized amplified filter circuit. The output filter circuit is coupled to the chopper stabilized amplified filter circuit and is configured to receive and filter the low pass filtered signal and in accordance therewith provide a filtered output data signal in which the out of band signal frequency component is substantially reduced in magnitude. The ADC circuit is coupled to the output filter circuit and is configured to receive and convert the filtered output data signal and in accordan

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