Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
2003-03-26
2004-10-26
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S262000
Reexamination Certificate
active
06809580
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on and incorporates herein by reference Japanese patent application No. 2002-117603 filed on Apr. 19, 2002.
FIELD OF THE INVENTION
The present invention relates to a switched capacitor filter circuit and a method of fabricating the circuit. Specifically it relates to the switched capacitor filter circuit that can reduce feedthrough noise and the method of fabricating the circuit.
BACKGROUND OF THE INVENTION
Various switched capacitor circuits are proposed.
A switched capacitor integration circuit shown in
FIG. 10A
is configured with an operational amplifier
403
, an input capacitor
404
, switching circuits
405
,
406
, and an integration capacitor
407
. An input voltage Vin is inputted to an inverting input terminal of the operational amplifier
403
via the input capacitor
404
and the switching circuit
406
, and an output terminal of the operational amplifier
403
is connected to the inverting input terminal via the integration capacitor
407
.
The switching circuits
405
,
406
simultaneously switch the ground potential and the signal path side with a switching control signal (not shown). The signal path side is the path extended to the inverting input terminal of the operational amplifier
403
via the input capacitor
404
from the input terminal to which the input voltage Vin is impressed. First, when the switches
405
,
406
are connected to the ground, the input capacitor
404
is discharged. Next, the switching circuits
405
,
406
are connected to the signal path side, the input voltage Vin is impressed to the switching circuit
405
of the input capacitor
404
, and the input capacitor
404
is charged. When the switching circuits
405
,
406
are switched to the ground, the input capacitor
404
is discharged.
Assuming that capacitance of the input capacitor
404
is C
1
and an amount of charge stored in the input capacitor
404
is Q, the amount is expressed as Q=C
1
·Vin. Also assuming that a current flowing into the input capacitor
404
is i′, a switching frequency of a switching control signal (sampling frequency) is fs, and a switching period of the switching control signal is T=1 /fs. This current is expressed as i′=Q·fs=C
1
·Vin·fs=(C
1
·Vin)/T. As understood from this expression, due to the switching operations of the switching circuits
405
,
406
, the current i′ flows during a period of the switching control signal (not shown). Therefore this circuit may be considered as a resistor for the input signal of sufficiently lower frequency to the frequency fs of the switching control signal.
Assuming the switching circuit
405
, capacitor
404
, and switching circuit
406
in
FIG. 10A
are assumed to be equivalent to a resistor
401
of an analog integration circuit composed of an operational amplifier
400
and an integration capacitor
402
shown in
FIG. 10B
, that is, i=i′, the relationship of R=T/C
1
=1/(fs·C
1
) is obtained. Also, assuming that capacitance of the integration capacitor
407
in
FIG. 10B
is C
2
, cut-off frequency f
0
is expressed as f
0
=1/(2&pgr;R·C
2
)=(fs·C
1
)/(2&pgr;C
2
). As described above, the switched capacitor filter circuit is capable of controlling the cut-off frequency f
0
with a capacitance ratio of the sampling frequency fs to the input capacitor
404
and integration capacitor
407
. Therefore, unlike a large capacitor and an RC filter which are required to have a large scale capacitor or higher accuracy of capacitance, the switched capacitor filter circuit is suitable for integration.
The switched capacitor circuit is used for a first-order filter as shown in FIG.
11
. This first-order filter is configured with switching transistors
100
to
107
, an input capacitor
110
, a limit capacitor
111
, an integration capacitor
112
, and an operational amplifier
113
.
One terminal of the input capacitor
110
is connected to an input terminal IN via the switching transistor
100
and also connected to an internal reference voltage terminal REF (indicated as an inverted triangle) via the switching transistor
104
, while the other terminal is connected to an inverting input terminal of the operational amplifier
113
via the second switching transistor
101
and also connected to the internal reference voltage terminal REF via the switching transistor
105
. One terminal of the limit capacitor
111
is connected to the inverting input terminal of the operational amplifier
113
via the switching transistor
102
and is also connected to the internal reference voltage terminal REF via the switching transistor
106
. The other terminal is connected to an output terminal OUT via the switching transistor
103
and also connected to the internal reference voltage terminal REF via the switching transistor
107
. One terminal of the integration capacitor
112
is connected to the inverting input terminal of the operational amplifier
113
. The other terminal is connected to an output terminal. It is assumed here that the voltage of input terminal IN is V
1
, the voltage of the inverting input terminal of the operational amplifier
113
is V
2
, and the output voltage of the operational amplifier
113
is V
3
.
With this configuration, the switching transistors
100
to
107
are turned on or off with switching control signals (control signals) &phgr;
1
, &phgr;
2
shown in FIG.
12
. The switching transistors
100
to
103
turn on when the control signal &phgr;
1
is high level, while the switching transistors
104
to
107
turn on when the control signal &phgr;
2
is high level.
When the control signal &phgr;
1
is low level and the control signal &phgr;
2
is high level, the input capacitor
110
is grounded via the switching transistors
104
,
105
, while the limit capacitor
111
is grounded via the switching transistors
106
,
107
and are then discharged. Under this condition, when both control signals &phgr;
1
, &phgr;
2
are in the low level state, the switching transistors
100
to
107
are all turned off, and thus no currents flow into the input capacitor
110
and the limit capacitor
111
.
When the control signal &phgr;
1
becomes high level and the control signal &phgr;
2
becomes low level, the switching transistors
100
to
103
are turned on, so that a charging current flows into the input capacitor
110
depending on a voltage difference (V
1
−V
2
) applied across both terminals, and thereby the input capacitor
110
is charged up to the voltage depending on the voltage difference (V
1
−V
2
). Charging current flows into the integration capacitor
112
depending on a voltage difference (V
2
−V
3
) applied across both terminals and thereby the integration capacitor
112
is charged up to the voltage depending on the voltage difference (V
2
−V
3
).
When both control signals &phgr;
1
, &phgr;
2
become low level, the switching transistors
100
to
103
are turned off, so that no currents flow into the input capacitor
110
and the limit capacitor
111
.
As described above, the input capacitor
110
and the limit capacitor
111
become the circuit where predetermined current flows during a period of the control signals &phgr;
1
, &phgr;
2
. Therefore it may be considered to be equivalent respectively to resistors. The integration capacitor
112
is charged depending on the voltage difference (V
2
−V
3
) applied across both terminals thereof regardless of switching operations in the switching transistors
100
to
107
.
The switched capacitor filter circuit in
FIG. 11
can be thought, for an input signal of sufficiently lower frequency to the sampling frequency, to be equivalent to a first-order low pass filter as shown in FIG.
13
. In this filter, the input capacitor
110
and its associated transistors
100
,
101
,
104
and
105
are represented as a resistor
120
, while the limit capacitor
111
and its associated transistors
102
,
103
,
106
and
107
are represented as a resistor
130
.
As a swi
Aoyama Seiki
Itakura Toshikazu
Denso Corporation
Le Dinh T.
Posz & Bethards, PLC
LandOfFree
Switched capacitor filter circuit and method of fabricating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Switched capacitor filter circuit and method of fabricating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Switched capacitor filter circuit and method of fabricating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3303403