Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-06-13
2002-12-31
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S146000
Reexamination Certificate
active
06501409
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to broadband telecommunications. More particularly, the present invention relates to a circuit interfacing a digital-to-analog converter (DAC) and a continuous-time reconstruction filter in a broadband telecommunication system.
BACKGROUND OF THE INVENTION
FIG. 1
schematically illustrates a typical transmission path
10
for a broadband telecommunications system, such as an asymmetric digital subscriber line (ADSL) system. Digital data is sent from a digital signal processing (DSP) unit
12
, such as an encoder, to a digital-to-analog converter (DAC)
14
. The analog output of the DAC
14
represents a modulated signal that is to be transmitted on a transmission line
20
such as a telephone line (or twisted-pair copper line). Since the operation of an actual DAC is not ideal, the analog output of the DAC
14
generally contains a large amount of spurious, out-of-band harmonics generated by the zero-order hold nature of the DAC. Thus, a reconstruction filter
16
is used to reduce or substantially eliminate the out-of-band harmonics. The reconstructed transmit signal is input to a line driver
18
. The line driver
18
provides sufficient power to the signal to drive the transmission line.
FIG. 2
schematically illustrates the basic structure of a typical reconstruction filter
16
. As shown in
FIG. 2
, the reconstruction filter
16
is configured as a low-pass filter circuit, and includes an amplifier
26
, a feedback resistor Rf and a capacitor C. The output of the DAC
22
is input via an input resistor
24
to the amplifier
24
. However, since the operation of the DAC
14
is inherently discrete time in nature, its analog output is typically distorted from the ideal form of an impulse voltage signal shown in FIG.
3
A.
FIG. 3B
schematically illustrates an actual analog output of the DAC
14
. As shown in
FIG. 3B
, the actual analog output includes distortions such as stewing
27
and glitching
28
. In addition, a zero-order held waveform of the DAC
14
causes a frequency dependent droop across the output band, which requires a costly correction by means of digital processing before the DAC
14
or within the subsequent analog filter.
In order to solve these problems associated with the DAC analog output distortions, a reconstruction filter having an input sampling circuit was proposed in the U.S. Pat. No. 6,215,431, entitled DROOP-FREE QUASI-CONTINUOUS RECONSTRUCTION FILTER INTERFACE, issued on Apr. 10, 2001, which is hereby incorporated herein by reference as if set forth fully herein.
FIG. 4
schematically illustrates a typical reconstruction filter
30
having an input sampling circuit
32
. Instead of inputting the analog voltage signal via the input resistor
24
(FIG.
2
), the DAC output is resampled by the input sampling circuit
32
before being supplied to a low-pass filter portion
39
. As shown in
FIG. 4
, the input sampling circuit
32
includes a sampling capacitor
36
, a sampling switch
37
, and an input switch
38
.
By appropriately selecting the timings of the sampling switch
37
and the input switch
38
with respect to the clock signal of the DAC
34
, the analog voltage signal from the DAC
34
is sampled at the point where the DAC
34
has settled to the correct voltage level. The sampled voltage signal is stored in the sampling capacitor
38
and then is effectively “dumped” into the low-pass filter portion
39
as an impulse current signal.
FIG. 3C
schematically illustrates the current signal from the sampling circuit
32
input to the low-pass filter
39
. As shown in
FIG. 3C
, the impulse current signal approximates the ideal output signal of the DAC shown in FIG.
3
A.
FIG. 5
illustrates an example of circuit implementation of a reconstruction filter
40
with the resampling feature for a traditional switched-capacitor DAC
42
. As shown in
FIG. 5
, the conventional switched-capacitor voltage-mode DAC
42
includes a capacitor array
52
controlled by a digital word, and an amplifier
54
for converting the charge from the capacitor array into an analog voltage signal. The digital word is supplied via one or more DAC references
53
. The reconstruction filter
40
includes a sampling circuit
44
and a low-pass filter
46
. The low-pass filter
46
is of a quasi-continuous nature, including a switched capacitor
48
in its feedback path which is synchronized with the sampling capacitor
49
.
In a typical arrangement in the transmission path, as shown in
FIG. 5
, the switched-capacitor DAC
42
is followed by a reconstruction filter
40
. Thus, an amplifier is required for the DAC
42
to generate an analog voltage signal, as well as amplifiers required in the reconstruction filter
40
. However, more amplifiers consume more power in the system, and in some applications, power saving is very important. Accordingly, it would be desirable to provide an interface circuit for a reconstruction filter which can provide an impulse signal approximating the ideal DAC output and requires less power than prior art circuits.
BRIEF DESCRIPTION OF THE INVENTION
A circuit includes a switched-capacitor array for converting a digital signal into a corresponding amount of electric charge, a switching circuit, and a continuous-time reconstruction filter circuit. The switched-capacitor array includes a plurality of capacitors and a summing node to which the plurality of capacitors are connected. The switching circuit is coupled between the summing node and the continuous-time reconstruction filter circuit, and supplies a pulsed current signal to the continuous-time reconstruction filter circuit. The circuit may further include a gain stage coupled between the summing node and the switching circuit, for controlling a gain of the pulsed current signal. The gain stage may provide a variable gain. The gain stage may include a coupling capacitor which may be programmable. A digital signal is supplied to the switched capacitor array and converted into a corresponding amount of electric charge. The electric charge is supplied as a pulsed current signal to the continuous-time reconstruction filter circuit without converting into a voltage signal.
REFERENCES:
patent: 5798724 (1998-08-01), Myers
patent: 6201438 (2001-03-01), Nicollini et al.
patent: 6215431 (2001-04-01), Sheng et al.
Hung Chih-Jen
Lynn Lapoe
Sheng Samuel W.
LSI Logic Corporation
Thelen Reid & Priest LLP
Wamsley Patrick
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