Switched-capacitor circuitry with reduced loading upon...

Details Switched-capacitor circuitry with reduced loading upon... Switched-capacitor circuitry with reduced loading upon...

1999-08-05

2001-06-19

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06249240

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of analog circuitry, and is more specifically directed to switched-capacitor circuits.
In the field of analog circuits, such as implemented in modem analog and mixed-signal (i.e., containing both digital and analog functions) integrated circuits, switched-capacitor techniques are utilized in many applications. In general, switched-capacitor circuits operate by periodically connecting an input voltage to a capacitor, which in turn stores a charge corresponding to the applied voltage. The capacitor is subsequently connected to an input of an amplifier or other circuit to communicate the input voltage to downstream circuitry. As such, sample-and-hold functions are commonly realized by way of switched-capacitor techniques.
One important application of switched-capacitor techniques is the comparison of an input signal voltage to a reference voltage. In this application, the sampling capacitor is initially connected to a reference voltage, such as may be generated by a band-gap voltage reference circuit or similar circuit for generating a reference voltage that is relatively stable over variations in power supply voltage, temperature, and manufacturing process parameters. The capacitor is then switchably connected to receive a signal input voltage, such that the resulting charge on the capacitor corresponds to the differential between the signal input voltage and the reference voltage. This resulting charge can then be sensed by an amplifier, which in turn generates a signal corresponding to that differential. The reference voltage is then again connected to the sampling capacitor in preparation for the next sample of the input voltage.
This switched-capacitor comparator function is commonly used in many integrated circuit applications. One important use of this function is in pipelined analog-to-digital converter circuits (ADCs), an example of which is presented, in block diagram form, as ADC
10
of FIG.
1
. As illustrated therein, ADC
10
receives an analog input voltage on line V
IN
and generates, at its output, an n-bit digital word on lines V
OUT
that correspond to the input analog voltage. To accomplish this function, ADC
10
includes a series of analog stages
4
0
through
4
k
. First stage
4
0
receives the analog input voltage on line V
IN
and, based on the amplitude of this input voltage, generates an m-bit digital output on lines D
0
and a residue output on lines RES
0
. Typically, the number of digital bits m generated by each stage
4
is 2 or more. The residue voltage on line RES
0
corresponds to a remainder of the “division” carried out in the digitization operation. As shown in
FIG. 1
, each subsequent, lower-order, stage
4
j
(from the set of stages
4
1
through
4
k
) receives the residue voltage on lines RES
j−1
from the previous stage
4
j−1
, and similarly generates m digital output bits on lines D
j
, and a residue analog voltage on line RES
j
that is forwarded to the next stage
4
j+1
in the pipeline.
The digital results of each stage
4
j
are stored in corresponding latch
6
j
, the contents of which are summed, by adder
8
j
, with the digital result on lines D
j+1
from the next stage
4
j+1
in the sequence; the output of the final adder
8
k
is the n-bit digital output word on lines V
OUT
. The pipelining effect of ADC
10
is enabled by the operation of latches
6
; once a stage
4
j
derives a digital result and residue, it can begin conversion of the next sample in time while the next stage
4
j+1
operates on the result from the previous sample. As such, each of the multiple stages
4
in ADC
10
can be operating on different samples of the input signal voltage V
IN
, with a sequence of digital results generated by final adder
8
k
.
FIG. 2
illustrates the functional construction of exemplary analog stage
4
j
in ADC
10
of FIG.
1
. As shown in
FIG. 2
, input voltage V
in
is applied to sub-ADC
5
, which produces the digital output on lines D
j
; these digital outputs are also applied to sub-DAC
7
, which presents an analog signal to subtractor
9
. Subtractor
9
subtracts the output from sub-DAC
7
from the value of input voltage V
in
, sampled and held by sample-and-hold circuit
3
; the output of subtractor
9
is amplified by gain amplifier
11
to generate analog residue voltage on line RES
j
that is within a voltage range suitable for use by a next, downstream, analog stage
4
j+1
.
In typical modern pipelined ADCs, certain of the functions of each stage
4
are combined into single circuits, which may be realized according to switched-capacitor techniques. An example of such a conventional modern pipelined ADC may be found in Lewis, et al., “A 10-b 20 Msample/s Analog-to-Digital Converter”,
J. Solid State Circ
., Vol. 27, No. 3 (IEEE, March 1992), pp. 351-58. As described therein, the functions of sample-and-hold
3
, subtractor
9
, sub-DAC
7
, and amplifier
11
may be combined into a switched-capacitor amplifier circuit that operates upon differential input voltages, and a comparison against two reference voltage levels. In the ten-bit case of the Lewis, et al. article, each of nine stages receives two reference voltage levels at switched-capacitor inputs. As exemplified in the Lewis, et al., article, and as is known in the art, switched-capacitor pipelined ADC circuits provide excellent resolution at extremely high conversion rates, considering the pipelined architecture of the ADC.
Of course, as is known in the art, ADCs of 14-bit and 16-bit precision are now commonly used, with even higher precision ADCs expected in the near future. According to the typical switched-capacitor architecture, as described in the Lewis et al. article and as will now be described relative to
FIG. 3
, each switched-capacitor stage of the ADC performs a comparison of sampled differential input voltages, precharging sample nodes to reference voltages before each sample of the differential input signal. Accuracy in this comparison requires, of course, reference voltages that are not only stable over variations in power supply voltage, temperature, and manufacturing process parameters, but is also stable considering the switching operation of the ADC.
FIG. 3
illustrates an example of conventional differential switched-capacitor stage
15
j
as may be used in modem pipelined ADCs and other circuits that utilize switched-capacitor comparisons. For purposes of clarity, conventional devices that are commonly included to minimize charge injection current and apply precharge voltages at certain circuit nodes are not shown in FIG.
3
. In this example, switched-capacitor stage
15
j
receives a differential input voltage on lines V
in
+
and V
in
−
, and two reference voltage levels V
refp
and V
refn
. In operation, switched-capacitor stage
15
j
compares the voltage on line V
in
+
with the voltage on line V
in
−
, after precharging respective capacitor inputs to reference voltages V
refp
, V
refn
. Reference voltages V
refp
and V
refn
are generated by reference voltage circuit
20
which includes, in this conventional example, bandgap circuit
12
for generating a voltage on line V
r
that is stable over variations in power supply voltage, temperature, and manufacturing process parameters. Various implementations of bandgap circuit
12
are well known in the art. Line V
r
, in this example, is applied to an inverting input of operational amplifier
14
, which has its non-inverting input biased to ground. According to conventional circuit techniques, the resistive input and feedback arrangement of amplifier
14
, in combination with the capacitive coupling of the inverting and non-inverting outputs as illustrated, provide reference voltages V
refp
and V
refn
to switched-capacitor stage
15
j
and other similar stages (not shown) which remain stable over various parameter variations

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