Switched-capacitor circuit with time-shifted switching scheme

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

Reexamination Certificate

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Details

C327S096000, C327S337000

Reexamination Certificate

active

11258686

ABSTRACT:
A switched-capacitor circuit for sampling a pair of differential input signals includes a first bootstrapped switch and a first non-boosted switch connected in parallel between a first output terminal of an amplifier and a first feedback node of the switched-capacitor circuit to form a first feedback signal path and a second bootstrapped-switch and a second non-boosted switch connected in parallel between a second output terminal of the amplifier and a second feedback node of the switched-capacitor circuit to form a second feedback signal path. The first and second non-boosted switches are controlled by a first clock signal and the first and second bootstrapped switches are controlled by a second clock signal where the second clock signal is the first clock signal delayed by a predetermined amount.

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Dan Kelly et al., “A 3V 340mW 14b 75MSPS CMOS ADC with 85dB SFDR at Nyquist,” Analog Devices Inc., 2001 IEEE International Solid State Circuits Conference, 3 pages.

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