Switched-capacitor circuit with scaled reference voltage

Details Switched-capacitor circuit with scaled reference voltage Switched-capacitor circuit with scaled reference voltage

2006-03-07

2006-03-07

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S118000, C341S172000

Reexamination Certificate

active

07009549

ABSTRACT:
A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which includes a sample-and-hold circuit (22), an analog-to-digital converter (23), and the functions of a digital-to-analog converter (DAC) (25), an adder (24), and a gain stage (27) at which a residue signal (RES) is generated for application to the next stage (20) in the sequence. A multiplying DAC (28) performs the functions of the DAC (25), adder (24), and gain stage (27) in the stage (20), and is based on an operational amplifier (29). Sample capacitors (C10, C20) and reference capacitors (C122, C222) receive the analog input from the sample-and-hold circuit (22) in a sample phase; parallel capacitors (C121, C221) are provided to maintain constant circuit gain. Extended reference voltages (VREFPX,VREFNX) at levels that exceed the output range (V0+, V0−) of the operational amplifier (29) are applied to the reference capacitors, in response to the digital output of the analog-to-digital converter (23) in its stage (20). The reference capacitors (C12, C22) are scaled according to the extent to which the extended reference voltages (VREFPX,VREFNX) exceed the op amp output levels (V0+, V0−). The effects of noise on the reference voltages (VREFPX,VREFNX) on the residue signal (RES) are thus greatly reduced.

REFERENCES:
patent: 6249240 (2001-06-01), Ballaouar
patent: 6909391 (2005-06-01), Rossi
patent: 6909393 (2005-06-01), Atriss et al.
Abo et al., “A 1.5 V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter”, J. Solid State Circ., vol. 34, No. 5 (IEEE, May 1999), pp. 599-606.

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