Switched capacitor circuit having reduced capacitance units

Details Switched capacitor circuit having reduced capacitance units Switched capacitor circuit having reduced capacitance units

1993-11-22

1995-08-08

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

341153, H03M 180

Patent

active

054403065

ABSTRACT:
A switched capacitor circuit includes a first capacitor (102) connected between first and second nodes (101, 103), a second capacitor (C.sub.1) connected between the first node and an intermediate node (M), and a third capacitor (C.sub.2) connected between the intermediate node (M) and ground. A group of m parallel circuits are connected between the intermediate node and the second node. Each of the m parallel circuits has a fourth capacitor (C.sub.V) and a switch (D.sub.V) for coupling it to ground or to the second node (103) depending on a corresponding one of m bits of an N-bit gain control signal. (N-m) parallel circuits are connected between the first and second nodes, each including a fifth capacitor and a switch for charging it depending on one of (N-m) bits of the N-bit gain control signal. A first sampling switch (S.sub.1) couples an input voltage to the first node (101) in response to the first phase of a two-phase clock signal and coupling the first node to ground in response to the second phase. A second sampling switch provides charging of a sixth capacitor (104), connected to the second node, in response to the first phase and discharges energy from it to an output terminal of the switched capacitor circuit in response to the second phase.

REFERENCES:
patent: 4872011 (1989-10-01), Pelgrom et al.
patent: 4873525 (1989-10-01), Iida
patent: 5274376 (1993-12-01), Phillips et al.

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