Wave transmission lines and networks – Coupling networks – Frequency domain filters utilizing only lumped parameters
Reexamination Certificate
2003-12-02
2004-11-30
Lam, Tuan T. (Department: 2816)
Wave transmission lines and networks
Coupling networks
Frequency domain filters utilizing only lumped parameters
C333S184000, C327S554000, C327S565000
Reexamination Certificate
active
06825739
ABSTRACT:
The present invention relates to a switched capacitor circuit including a differential amplifier, especially to a switched capacitor circuit for highly accurate operation, the switched capacitor circuit being capable of reducing electrical power consumption, or having high-speed performance.
BACKGROUND OF THE INVENTION
Recited in “Analog MOS Integrated Circuits for Signal Processing” (published 1986, pages 513 to 524) is an arranging method and layout method for each component of a switched capacitor circuit
501
shown in
FIG. 17
, in order to realize high noise tolerance and highly accurate signal operation.
Specifically, as shown in
FIG. 18
, the switched capacitor circuit
501
is provided with an area A
503
between an area A
501
and an area A
504
. In the area A
501
, a differential amplifier AMP
501
is provided, while in the area A
504
, provided are clock lines for transmitting a clock signal &phgr;. In the area A
503
, switches SW
501
to SW
503
are provided. Further, between the areas A
503
and A
501
, arranged is an area A
502
in which capacitors Cf
501
and Cs
501
are provided.
In the arrangement, the clock lines, which are noise sources that supply a significant amount of noise (clock noise), and the differential amplifier AMP
501
, which is susceptible to noise, are separated by the capacitors (Cs
501
and Cf
501
) and the analog switches (SW
501
to SW
503
) which are provided between the clock line and the differential amplifier AMP
501
. With this arrangement, it is possible to protect the differential amplifier AMP
501
from the clock noise. Further, when another one or more switched capacitor circuits
501
are provided together with the switched capacitor circuit
501
, it is possible to arrange the plurality of switched capacitor circuits
501
in a vertical direction (a direction that makes a right angle with a direction in which the areas A
501
to area A
504
are aligned). In this way, it is possible to lay out a circuit including the plurality of switched capacitor circuits
501
so that the circuit will be so compact.
Further, as shown in
FIG. 19
, the switched capacitor circuit
501
, which is the prior art, is provided with the guard lines Lg
501
that are maintained at a ground level. The guard lines Lg
501
are provided so as to sandwich a line L
501
, which is arranged between an inverting input terminal T
501
m
of the differential amplifier AMP
501
and a switch SW
501
for resetting the inverting input terminal T
501
m
. This shields the line L
501
from noise so as to prevent the switched capacitor circuit
501
from noise, thereby avoiding a significant reduction in operational accuracy of the switched capacitor circuit
501
.
However, if only the layout method is applied, it is difficult to shield all the lines that may have high impedance. Thus, in this case, it is a problem that a switched capacitor circuit that operates in a sufficiently high accuracy is difficult to realize.
Moreover, it is difficult to have the guard lines Lg
501
in at a gate of an input transistor of the differential amplifier AMP
501
, on a line in a vicinity of the gate, and in a connection part of an analog switch, and the like location. In addition, if shield layers are provided so as to sandwich a line connecting the inverting input terminal T
501
m
and the switch SW
501
in a perpendicular direction of a substrate (vertical direction), a new conductive layer is necessary for the shield layers, thereby increasing manufacturing cost of the switched capacitor circuit
501
.
Furthermore, shielding both input terminals of the differential amplifier AMP
501
increases parasite capacitance between (a) each of the input terminals and (b) ground, so that the parasite capacitance will have a value that is not negligibly low, compared with capacitance of a capacitor for operation, such as the capacitor Cs
501
for input and the Cf
501
for integral calculus. This may result in significant deterioration in settling characteristics. Especially, when the capacitance of the capacitor is reduced so as to attain a high-speed operation, there is a high possibility that the setting characteristics will be deteriorated. Thus, it is necessary that the capacitor for operation have a large capacitance. Thus, it is difficult to compatibly attain improvement in operational accuracy, and reduction in electrical power consumption or the high-speed performance.
SUMMARY OF THE INVENTION
The present invention has an object of realizing a switched capacitor circuit compatibly capable of improving operational accuracy, and of reducing electric power consumption or of attaining a high-speed operation.
A switched capacitor circuit of the present invention, in order to attain the object, is so arranged that a signal line crossing one of the lines connected to both input terminals of a differential amplifier is so positioned as to cross the other of the lines, wherein the lines are positioned next to each other to each other (i) from the respective input terminals to respective cross-points between the signal line and the lines, or (ii) from the respective input terminals to respective vicinities of the cross-points.
With the above arrangement, a signal line crossing a non-inverting-side line (hereinafter, the wording, “non-inverting-side” indicates that a component with the wording is provided on a non-inverting side with respect to the differential amplifier) crosses an inverting-side line (hereinafter, the wording “inverting-side” indicates that a component with the wording is provided on an inverting side with respect to the differential amplifier). Thus, an interference that is identical to an interference from the signal line onto the non-inverting-side line via a parasite capacitance is given to the inverting-side line from the signal line via a parasite capacitance. Therefore, the interferences are caused to cancel out each other by the differential operation of the differential amplifier. Thereby, it is possible to compatibly attain the improvement of the operational accuracy and the low electric power consumption or the high-speed operation.
A switched capacitor circuit of the present invention, in order to attain the above object, is so arranged that each of the non-inverting-side switch and the inverting-side switch is made of a pair of first and second switches connected to each other in parallel, wherein in one of the areas, which is a first area, the non-inverting-side first switch and the inverting-side first switch are provided, and in the other of the areas, which is a second area, the non-inverting-side second switch and the inverting-side second switch are provided.
With the above arrangement, the non-inverting-side and inverting-side switches can be positioned to be nearer to each other, compared with an arrangement in which the non-inverting-side switch is provided in one of the areas (for example, in the first area), and the inverting-side switch is provided in the other of the areas (for example, the second area). Therefore, it is possible to improve matching accuracies between the non-inverting-side and inverting-side first switches and between the non-inverting-side and inverting-side second switches. As a result, it is possible to cause clock noise entering the respective terminal to cancel out each other by the differential operation of the differential amplifier, thereby compatibly attaining the improvement in the operational accuracy and the low electric power consumption, or the high-speed operation.
A switched capacitor circuit of the present invention, in order to attain the above object, includes a signal line crossing one of the non-inverting-side line and the inverting-side line, which connect input terminals of the differential amplifier with switches respectively for resetting the input terminals, and an inverting signal line, crossing the one of the non-inverting-side line and the inverting-side line, for receiving an inverting signal of a signal to be transmitted via the signal line.
With the above arrangement, in which the inverting signal of th
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