Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – By integrating
Reexamination Certificate
1999-03-05
2001-02-20
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific input to output function
By integrating
C327S538000, C323S316000
Reexamination Certificate
active
06191637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to bias circuits for switched capacitor circuits, and in particular, to bias circuits for switched capacitor circuits which compensate for process tolerances, temperature and clock frequency.
2. Description of the Related Art
In circuit applications involving switched capacitor circuits, the amplifiers are typically required to drive only capacitive loads which do not require much, if any, DC current. Accordingly, such amplifiers can be designed without a low impedance output stage, such as an emitter follower or source follower circuit. As a result of this design simplification, such amplifiers used in switched capacitor circuits typically have a high output impedance and are often referred to as “operational transconductance amplifiers” to differentiate them from operational amplifiers having low output impedance. Applications in which high output impedances are acceptable allow single-stage operational transconductance amplifiers to be used. Such amplifiers are typically folded-cascode or telescopic (i.e., unfolded cascode) designs.
Referring to
FIG. 1
, such an amplifier will typically have a single dominant pole, thereby making the unity gain bandwidth proportional to the ratio of the transconductance g
m
of the input stage and the load capacitance C
LOAD
. Accordingly, as represented in the graph of
FIG. 1
, this relationship between unity gain bandwidth frequency f
unity
, transconductance g
m
and load capacitance C
LOAD
can be expressed by Equation (1) below.
f
unity
∝
g
m
C
LOAD
(
1
)
If the input differential pair of transistors (metal oxide semiconductor field effect transistors, or MOSFETs) of the operational transconductance amplifier are biased in the subthreshold region, then the input stage transconductance g
m
is inversely proportional to the product of Boltzmann's constant k and absolute temperature T divided by charge q. Accordingly, it follows that the input stage transconductance g
m
, using equations 2, 3 and 4 below, can be found using the drain current I
D
, majority carrier mobility &mgr;, gate oxide capacitance per unit area C
ox
, channel width W and length L, gate-to-source voltage V
GS
, threshold voltage V
T0
, source voltage V
S
and number n of output devices.
If
I
D
⪡
β
·
(
kT
q
)
2
where
β
=
μ
C
ox
W
L
(
2
)
Then
I
D
=
β
(
kT
q
)
2
ⅇ
(
(
V
GS
-
V
T0
-
nV
s
)
nkT
q
)
(
3
)
g
m
=
∂
I
D
∂
V
GS
=
I
D
nkT
q
(
subthreshold
)
(
4
)
Equations (1) and (4) can be combined to express the unity gain bandwidth frequency f
unity
according to Equation (5).
f
unity
∝
I
D
nkT
q
·
C
LOAD
(
5
)
As seen in Equation (5), if the drain current I
D
can be made proportional to the product of absolute temperature T and load capacitance C
LOAD
, the unity gain frequency f
unity
will be constant for all process and temperature variations. Ideally, the unity gain frequency f
unity
of the operational transconductance amplifier should track the frequency of the clock signal (with clock signal period T
clock
) for the switched capacitor filter. Accordingly, relations for the unity gain frequency f
unity
and drain current I
D
can be expressed according to Equations (6) and (7) below.
assuming
f
unity
∝
1
T
clock
(
6
)
then
I
D
∝
nkT
q
·
C
LOAD
T
clock
(
7
)
As should be recognized, the quotient of load capacitance C
LOAD
and clock signal T
clock
in Equation (7) is the approximate expression for a switched capacitor resistor equivalent.
Referring to
FIG. 2
, many conventional designs generate a PTAT (proportional to absolute temperature) bias current by developing a “difference voltage” across a resistor, where such “difference voltage” is the difference between the forward biased junction voltages of the diodes D
21
, D
22
. When the bias current lout generated by this circuit is substituted into Equation (4), the relationship for the subthreshold MOSFET transconductance g
m
can be expressed according to Equation (8) below.
g
m
=
I
D
nkT
q
=
ln
(
A
)
n
·
R
(
subthreshold
)
(
8
)
According to Equation (8), if the resistor R has no temperature dependance, the transconductance g
m
will be constant. Based upon this, it can then be shown that the unity gain frequency f
unity
of the operational transconductance amplifier can be expressed according to Equation (9).
f
unity
∝
ln
(
A
)
n
·
R
(
1
+
aT
+
bT
2
)
·
C
LOAD
(
9
)
According to Equation (9), the unity gain frequency f
unity
and the settling of the operational transconductance amplifier is a function of the absolute tolerances of the resistor R (typically within a range of ±20%) and the load capacitance C
LOAD
(typically within a range of ±10%). Assuming a linear resistor temperature coefficient equal to +700 ppm/° C. and a temperature range of −40° C. to +85° C., the overall tolerance of the unity gain frequency will be within a range of ±40%. This implies that in order to guarantee that the operational transconductance amplifiers (which are biased by the circuit of
FIG. 2
) will meet minimum settling time requirements, the bias current must be 40% larger than what would otherwise be considered optimum.
Referring to
FIG. 3
, another conventional design provides a compensated reference current Iref which is a function of a reference voltage Vref, a capacitance C and clock signal period Td. (This circuit is described in more detail in E. A. Vittoz, “The Design of High-Performance Analog Circuits on Digital CMOS Chips,” IEEE Journal of Solid-State Circuits, Vol. SC-20, no. 3, June 1985, pp. 657-65.) This circuit forms a servo loop in which, during one clock phase Td, capacitor C is charged to the reference voltage Vref and transistor M
1
drains charge from capacitor Cs which is equal to the product of the reference current Iref and the clock period Td.
During the next clock phase, capacitors C and Cs are shorted together and also connected to the inverting input of the operational amplifier. If the charge drained from capacitor Cs by transistor M
1
was more than that which is now available via charge sharing from capacitor C (i.e., the product of the reference voltage Vref and capacitance C), then the inverting input of the operational amplifier will be pulled to a lower potential which, in turn, will cause the gate terminal of transistor M
4
to be pulled to a higher potential, thereby reducing the magnitude of the reference current Iref (due to the current mirror action of transistors M
3
and M
5
).
This circuit has a number of disadvantages. This circuit requires a separate voltage reference circuit, the accuracy of the charge transfer (and power supply rejection) from capacitor C to capacitor Cs is sensitive to switch charge injection, and the value of the reference current is sensitive to the clock period Td. Additionally, this circuit is sensitive to parasitic capacitances on the top plates of capacitors C and Cs. Stray capacitances on these nodes will become discharged when the voltage changes during different clock cycles.
Referring to
FIG. 4
, another conventional design operates in an “open loop” manner and does not use any feedback. (This design is discussed in more detail in Olesin et al., U.S. Pat. No. 4,374,357, the disclosure of which is incorporated herein by reference.) In this design, capacitors C
22
and C
40
are alternately charged and discharged by transistors M
18
, M
20
, M
36
and M
38
during successive states of the clock signal. An average current equal to the product of the capacitance of capacitor C
22
(or capacitor C
40
since they are equal), the reference voltage Vref and two times the frequency of the clock signal (=C
22
*Vref*2*f
clock
) flows th
Ju Shu-Ing
Lewicki Laurence Douglas
Baker & McKenzie
National Semiconductor Corporation
Wells Kenneth B.
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