Electrical transmission or interconnection systems – Capacitor
Reexamination Certificate
2000-12-05
2004-06-22
Sircus, Brian (Department: 2836)
Electrical transmission or interconnection systems
Capacitor
C307S110000, C363S059000
Reexamination Certificate
active
06753623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to power converter circuits and, in particular, to switched capacitor array circuits used in DC—DC converters.
2. Description of Related Art
Switched capacitor circuitry is used in several power converter applications and is particularly advantageous where the use of inductors is to be avoided. In a typical application, switched capacitor circuitry is used to convert a D.C. input voltage to one or more D.C. output voltages which may differ in magnitude and polarity from the input voltage. In some instances the circuitry includes some form of voltage regulation for controlling the magnitude of the output voltage notwithstanding changes in magnitude of the input voltage and changes in the load driven by the circuitry.
FIGS. 1A
,
1
B,
1
C and
1
D depict various states of a conventional capacitor array of the type which can be used in an integrated circuit voltage regulator, such as the conventional DC—DC voltage converter shown in FIG.
3
. The converter includes a capacitor array circuit
10
comprised of three discrete capacitors A, B and C and several transistor switches which switch the capacitors into various configurations, such as those shown in
FIGS. 1A
,
1
B,
1
C and
1
D.
As is well known, the capacitor array is switched between two states or phases so that the capacitors will be charged on one of the phases by a power source and so that the charge is transferred to a load in another of the phases. In some configurations, the power source operates to charge the array and the charge is transferred to the load in one or both of the two phases.
FIG. 1A
is referred to as the common phase configuration of the capacitor array comprising capacitors A, B, C and the associated transistor switches (not depicted).
FIGS. 1B
,
1
C and
1
D are referred to as first, second and third gain phase configurations of the capacitor array. In operation, switch control circuitry
12
(
FIG. 3
) cause the array
10
to periodically switch between the common phase configuration (
FIG. 1A
) and one of the three gain phase configurations (
FIGS. 1B
,
1
C and
1
D). Thus, charge is periodically transferred from a power source (Vin) to a load connected to output Vsc.
The ratio Gsc of the output voltage Vsc of the capacitor array to the input voltage Vin is the gain state value of the array and is expressed as follows:
Gsc=Vsc/Vin
(1)
Gsc is based upon the output voltage Vsc when no load is connected to the array output other than a holding capacitor H. When a load is connected, voltage Vsc is reduced to the output voltage Vout, with the difference between Vout and Vsc being a function of, among other things, the net current delivered to the load.
Assuming that the gain phase configuration of the capacitor array is
FIG. 1B
, the value of Gsc can be determined by inspection. During the common phase configuration (
FIG. 1A
) the voltages across the three capacitors, V
A
, V
B
and V
C
are all equal to Vsc as follows:
V
A
=V
B
=V
C
=Vsc
(2)
Note that the “+” sign on the capacitors identifies the capacitor terminal and not necessarily the polarity of the voltage across the capacitor. The input voltage Vin is, by inspection, as follows:
Vin−Vsc+
(
V
A
+V
B
+V
C
) (3)
By combining equations (2) and (3), Vin=4Vsc so that Gsc is as follows:
Gsc=Vsc/Vin=
¼ (4)
Assuming that the
FIG. 1C
gain phase configuration is used, the input voltage Vin is, by inspection, as follows:
Vin=Vsc+
(V
A
+V
B
) (5)
By combining equations (2) and (5), Vin=3Vsc so that Gsc is as follows:
Gsc=Vsc/Vin=
⅓ (6)
A similar analysis will confirm that the third gain phase configuration shown in
FIG. 1D
will produce a gain Gsc=½. Thus, all of the gains for the
FIGS. 1A-1D
array produce an output Vsc which is smaller than the input Vin.
Referring to
FIG. 3
, the converter utilizes a switched capacitor array
10
, such as the array of
FIGS. 1A-1D
. The switch control circuitry
12
operates to control the state of the various transistor switches that are present in array
10
so that the array can assume any one of the configurations depicted in
FIGS. 1A-1D
. Gain setting circuitry
14
operates to control the switch control circuitry
12
so that the array will switch between the common phase configuration of
FIG. 1A and a
selected one of the gain phase configurations
1
B-
1
D so as to provide three gain state values, with Gsc=½, ⅓ and ¼.
A clock circuit
20
provides a clock signal used by the switch control circuitry
12
to switch the transistor switches in array
10
with non-overlapping clock signals. One phase of the clock signal operates to turn off selected ones of the transistor switches and the second phase operates to turn on selected ones of the switches. The frequency F at which the switched capacitor array
10
switches between the common and the gain phase configurations will determine the effective output impedance Zout of the array as follows:
Zout ∝
1/(
FC
) (7)
where C is the capacitance of the capacitors A, B and C. Thus, the output voltage Vout can be controlled by varying the value of the switching frequency F which will vary the voltage drop across Zout.
Regulation can be maintained only if a minimum gain state is maintained as will be explained.
Array
10
is capable of assuming different gain state values Gsc to increase the efficiency of the converter. The efficiency Eff of the converter can be generally expressed as follows:
Eff=Vout/
(
Gsc*Vin
) (8)
Thus, it can be seen that efficiency can be increased by using the smallest gain state value Gsc available, provided a minimum gain requirement is met. The gain state value Gsc must be at least large enough to ensure that the product of Gsc and Vin is larger than the desired output voltage. If this minimum gain requirement is not met, regulation of a voltage converter using the array cannot be carried out, as will be explained below in connection with equation (9).
The gain setting circuitry
14
of the
FIG. 3
converter causes array
10
to change from one gain state value Gsc to another. The switch driver circuitry permits changes in gain state value to be made only when the array is in the common phase configuration. Thus, for example, when Gsc changes from ⅓ to ½, the switch over occurs when the array is in the common phase configuration of
FIG. 1A
rather than going directly from the gain phase configuration of
FIG. 1C
(Gsc=⅓) to the gain phase configuration of
FIG. 1D
(Gsc=½).
Referring back to
FIG. 3
, a voltage reference circuit
26
produces reference voltage Vod indicative of the desired regulated output voltage Vout of the converter circuit. This value Vod is compared by a comparator circuit
24
with the actual output voltage Vout. The comparator output, sometimes referred to as signal Skip, has an average value inversely proportional to the load current provided by the converter circuit. Signal Skip is used to clock an up/down counter
16
which controls the gain setting circuitry
14
. The up/down counter
16
has three output states that set the gain of the switched capacitor array
10
to one of the 3 gain state values (Gsc=½, ⅓ or ¼).
The output of the comparator circuit
24
is also used to control the state of logic circuitry represented by AND gate
18
. As will be explained, gate
18
operates to either transfer or momentarily block the non-overlapping clock signals to the switch control circuitry
12
thereby controlling the amplitude of Vout by varying the value of Zout in accordance with equation (7). The switched capacitor array
10
must be in a gain state value Gsc which will be sufficiently large to permit voltage regulation. This is referred to as the minimum gain state val
Guenot Stephane
Kotowski Jeffrey P.
McIntyre William James
Deberadinis Robert L.
Girard & Equitz LLP
National Semiconductor Corporation
Sircus Brian
LandOfFree
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