Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-04-20
2001-05-29
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S535000, C326S033000, C326S034000
Reexamination Certificate
active
06239649
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to means for dynamically altering the threshold voltage of Silicon-On-Insulator (SOI) transistors, and more particularly to the application of SOI transistor unit cells in large scale integrated logic circuits to provide high performance, low power integrated circuits incorporating SOI transistor devices with adjustable threshold voltages.
2. Background Art
It is known that threshold voltages of SOI devices can be altered by changing the body-source bias potential. References that relate generally to adjusting the bias voltage of CMOS devices or to SOI devices and their application are as follows.
U.S. Pat. No. 5,610,533 issued to Arimoto et al. discloses a semiconductor circuit that converts body bias potential between first and second values for MOS-FET logic circuits.
U.S. Pat. No. 5,608,344 issued to Marlow discloses an analog double-throw switch that connects the body of a FET to either a first voltage or a second voltage.
U.S. Pat. No. 5,557,231 issued to Yamaguchi et al. discloses a semiconductor device in combination with a first bias voltage generating circuit for generating a first substrate bias voltage value for reducing power consumption in the standby state and a second bias voltage generating circuit for generating a second substrate bias voltage value for increasing operating speed in the active state.
U.S. Pat. No. 5,552,723 to Shigehara et al. discloses a body bias switch for MOSFET devices with two N channel FETs, one with a common gate with the FET being controlled, the other FET with a gate controlled by the complement of the signal at the gate of the FET being controlled.
U.S. Pat. No. 5,461.338 issued to Hirayama et al. discloses a circuit with a plurality of transistors on a substrate and a bias voltage generating circuit for providing a low threshold bias voltage in the active state for high speed operation and a high threshold bias voltage for power consumption the standby state.
U.S. Pat. No. 4,809,056 to Shirato et al. discloses a technique for fabricating an improved contact region of a SOI structure.
U.S. Pat. No. 5,185,535 to Farb et el. discloses separately controllable and independent back bias for adjacent CMOS transistors fabricated on SOI substrates.
Other background references include U.S. Pat. No. 5,594,371 to Douseki, U.S. Pat. No. 5,602,790 to Mullarkey, U.S. Pat. No. 5,546,020 to Lee et al., U.S. Pat. No. 5,317,181 to Tyson, U.S. Pat. No. 5,422,583 to Blake et al., U.S. Pat. No. 4,612,461 to Sood, U.S. Pat. No. 4,791,316 to Winnerl et al., U.S. Pat. No. 5.045,716 to Takacs et al., U.S. Pat. No. 5,103,277 to Caviglia et al., and U.S. Pat. No. 5,341,034 to Matthews.
SUMMARY OF THE INVENTION
Current CMOS technology continues to scale lower voltages and smaller dimensions. Presently there exists 3.5 volt and 2.5 volt operation, and 1.8 volt operation is anticipated. However, the scaling of threshold voltage is becoming increasingly difficult. If threshold voltage is not scaled with power supply voltage, then the performance is effected because of low active current. If the threshold voltage is scaled to low values, the transistors exhibit a high leakage current in the off state. In addition, data shows that alpha particle sensitivity increases with lower voltage, making it more difficult to design stable logic functions, shift register latches and memory storage cells.
One solution is to change from bulk CMOS devices to devices in Silicon On Insulator (SOI) substrates. SOI substrates exhibit lower alpha particle sensitivities because of smaller capture cross sections. However, impact ionization results in greater overall alpha particle sensitivity above 1.75 volts. Below 1.75 volts, alpha particle sensitivity relative to bulk CMOS decreases significantly because of the large reduction of impact ionization, which can be one or more orders of magnitude differences at 0.75 volts.
An object of the present invention is to provide switched body SOI CMOS circuits having an FET device that is switched from a floating body condition to a bias condition to raise the FET device threshold voltage after switching.
Another object of the present invention is to provide a switched body SOI CMOS circuit with circuit control of FET device wells for increased on/off current ratio.
Still another object of the present invention is to provide a switched body SOI unit cell structure in which the gate terminal of an FET controls the connection of the body bias to the FET body.
A further object of the present invention is to provide a switched body SOI device that has a low threshold voltage level in the active switching state and a high threshold voltage level in the standby state.
A still further object of the present invention is to provide a switched body SOI unit cell structure wherein the source-body voltage is controlled separately during different operating regimes of SOI FET devices.
A still further object of the present invention is to provide switched body SOI CMOS unit cell structures having FET devices with threshold voltage levels that can be altered by changing the body source potential.
Still another object of the present invention is to provide switched body SOI devices that have a low threshold voltage level in the active switching state and a high threshold voltage level in the standby state.
Still another object of the present invention is to provide switched body SOI unit cell structures that are switched between a low voltage level floating body condition to a bias condition that raises the threshold voltage level after switching.
A further object of the present invention is to provide an switched body SOI unit cell structures wherein the source-body voltage is controlled separately during different operating regimes of SOI FET devices.
A still further object of the present invention is to provide an improved method of fabricating an SOI device according to the principles of the present invention.
Still another object of the present invention is to provide a complementary pass gate logic circuit including SOI unit cells according to the principles of the present invention.
Still another object of the present invention is to provide a latch circuit including SOI unit cells according to the principles of the present invention.
Other features, advantages and benefits of the present invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings which are incorporated in and constitute a part of this invention and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure.
REFERENCES:
patent: 4612461 (1986-09-01), Sood
patent: 4791316 (1988-12-01), Winnerl et al.
patent: 4809056 (1989-02-01), Shirato et al.
patent: 5045716 (1991-09-01), Takacs et al.
patent: 5103277 (1992-04-01), Caviglia et al.
patent: 5157279 (1992-10-01), Lee
patent: 5185535 (1993-02-01), Farb et al.
patent: 5191244 (1993-03-01), Rundaldue et al.
patent: 5317181 (1994-05-01), Tyson
patent: 5341034 (1994-08-01), Matthews
patent: 5422583 (1995-06-01), Blake et al.
patent: 5461338 (1995-10-01), Hirayama et al.
patent: 5546020 (1996-08-01), Lee et al.
patent: 5550486 (1996-08-01), Sweeney et al.
patent: 5552723 (1996-09-01), Shigehara et al.
patent: 5557231 (1996-09-01), Yamaguchi et al.
patent: 5594371 (1997-01-01), Douseki
patent: 5602790 (1997-02-01), Mullarkey
patent: 5608344 (1997-03-01), Marlow
patent: 5610533 (1997-03-01), Arimoto et al.
patent: 5612643 (1997-03-01), Hirayama
patent: 5748029 (1998-05-01), Tomasini et al.
patent: 5939936 (1999-08-01), Beiley et al.
patent: 5966043 (1999-10-01), Jinbo
Bertin Claude Louis
Ellis-Monaghan John Joseph
Hedberg Erik Leigh
Hook Terence Blackwell
Mandelman Jack Allan
Callahan Timothy P.
Goodwin John J.
International Business Machines - Corporation
Luu An T.
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