Amplifiers – With periodic switching input-output
Reexamination Certificate
2001-08-20
2003-05-06
Nuton, My-Trang (Department: 2816)
Amplifiers
With periodic switching input-output
Reexamination Certificate
active
06559716
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a switchable operational amplifier for switched op amp technology, as well as a method for operating an operational amplifier of this sort.
Switched op amp technology was developed from switched capacitor technology in order to meet the need for ever-lower supply voltages. In switched op amp technology, not only the capacitors, but also the operational amplifier itself is periodically switched on and off using a switching signal. Since each operational amplifier is switched off during approximately 50% of the operating time, a considerable savings in power can be realized using switched op amp technology. Switched op amp technology is suitable in particular for applications in which a low supply voltage and a low power consumption are important, thus, for example for filters, transformers, converters or transducers in mobile radio devices, and for medical purposes (pacemakers, hearing aids), etc.
For use in switched op amp circuits, switchable operational amplifiers are known in which the end stage can be periodically switched on and off using an additional transistor.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a switchable operational amplifier for switched op-amp applications which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which enable an additional reduction of the power consumption of switched op amp circuits.
With the foregoing and other objects in view there is provided, in accordance with the invention, a switchable operational amplifier for switched op amp technology. The operational amplifier includes an end stage periodically switched on and off by a switching clock signal, and a pre-stage connected to the end stage and has a device for reducing a current through the pre-stage. The device reduces the current flowing through the pre-stage during an off phase of the switching clock signal from a first value to a smaller second value.
The inventive switchable operational amplifier has a pre-stage as well as an output or end stage, whereby the end stage can be periodically switched on and off through a switching clock signal. The inventive switchable operational amplifier has a device for reducing the current through the pre-stage, which reduces the current flowing through the pre-stage during the off phase of the switching clock signal switching from a first value to a smaller second value.
During the off phase of the switching clock signal, not only is the current through the end stage switched off, but in addition the current through the pre-stage is also lowered. Through this measure, an additional savings of power can be achieved over the known switchable operational amplifiers, in which the pre-stage also remains switched on during the off phase of the switching clock signal, and therefore constantly consumes current. In order to control the periodic variation of the current through the pre-stage, the same switching clock signal can be used that also periodically switches the end stage on and off. For this reason, the inventive solution can be realized with a low additional circuit outlay.
According to an advantageous specific embodiment of the invention, the device for reducing the current through the pre-stage, switches off the current flowing through the pre-stage during the off phase of the switching clock signal. The complete switching off of the pre-stage during the off phase of the switching clock signal represents the simplest and most economical specific embodiment of the invention. With this solution, the highest possible power savings can be achieved.
Here it is advantageous if the device for reducing the current through the pre-stage includes at least one transistor that switches off the current flowing through the pre-stage during the off phase of the switching clock signal. For the realization of the invention, one additional transistor is sufficient that is clocked by the switching clock signal and that periodically switches the pre-stage on and off. The expense for additional components can therefore be kept very low in this specific embodiment.
According to an alternative specific embodiment of the invention, the device for reducing the current through the pre-stage includes at least one pair of transistors connected in parallel. During the switched-on phase of the switching clock pulse, a first fraction of the current flowing through the pre-stage flows through the respective first transistors of the pair or pairs, and a second fraction of the current flowing through the pre-stage flows through the respective second transistors of the pair or pairs. The overall current through the pre-stage is therefore split in such a manner that a part of the current flows through the first transistors, and the remaining part of the current flows through the second transistors of the pair or pairs. During the off phase of the switching clock signal, the respective second transistors are then switched off. In this way, the overall current flowing through the pre-stage is reduced to the first fraction flowing through the first transistors.
The current portions flowing via the respective transistors depend on the ratio W/L, i.e., the ratio of width to length, of the devices used. In this way, it is possible to set which fraction of the overall current is switched off during the off phase of the switching clock signal. The currents flowing via the first transistors and via the second transistors can however also be set using the bias voltage that is present at the gate of the switching FETs.
The splitting of the overall current has the advantage that a certain flow of current through the pre-stage is maintained even during the off phase of the switching clock signal. In comparison with the complete switching off of the pre-stage, in this way a better activation performance can be achieved. Given higher circuit requirements, it is therefore advantageous not to completely shut off the current through the pre-stage. Given correspondingly smaller dimensioning of the current flowing during the off phase, the power savings is still considerable.
According to another advantageous specific embodiment of the invention, the pre-stage is realized as a convoluted or folded pre-stage having an input branch and an output branch. During the off phase of the switching clock signal, the device for reducing the current through the pre-stage reduces the current flowing in the input branch and/or the current flowing in the output branch.
The use of a convoluted pre-stage having an input branch and an output branch is advantageous in particular in the case of low supply voltages. The current difference occurring in the input branch is transferred 1:1 to the output branch. With a convoluted pre-stage, a high signal level swing at the output of the pre-stage can be achieved even with a low supply voltage.
Given a convoluted pre-stage, there is a flow of current in the input branch of the pre-stage and also a flow of current in the output branch of the pre-stage. If the inventive configuration of a current reduction during the off phase of the switching clock pulse is now applied to a convoluted pre-stage, then either the current flowing in the input branch of the pre-stage or the current flowing in the output branch of the pre-stage can be reduced. The highest power savings is achieved if the current is reduced in both branches.
For this purpose, it is advantageous if the input branch of the pre-stage includes at least one pair of transistors connected in parallel, whereby during the switched-on phase of the switching clock signal a first fraction of the current flowing through the input branch flows through the respective first transistor(s) of the pair or pairs, and a second fraction of the current flowing through the input branch flows through the respective second transistor(s) of the pair or pairs. During the switched-on phase of the switching clock signal, the overall current through the input branch is therefo
Sauerbrey Jens
Wittig Martin
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nuton My-Trang
Stemer Werner H.
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