Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Patent
1989-09-13
1991-06-11
Pellinen, A. D.
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
341136, 341118, H03M 166, H03M 106
Patent
active
050236148
ABSTRACT:
In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma
sec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse bias potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.
REFERENCES:
patent: 4716398 (1987-12-01), Eccleston et al.
patent: 4716463 (1987-12-01), Stacy et al.
patent: 4766415 (1988-08-01), Dielacher
patent: 4839530 (1989-06-01), Greenwood
patent: 4926064 (1990-05-01), Tapang
An Jiu
Campbell David L.
Fung Jimmy
Shyu Steven
Advanced Micro Devices , Inc.
Logan Sharon D.
Pellinen A. D.
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