Switchable clock circuit for microprocessors to thereby save pow

Details Switchable clock circuit for microprocessors to thereby save pow Switchable clock circuit for microprocessors to thereby save pow

1992-03-27

1993-10-19

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307443, H03R 19003

Patent

active

052548880

ABSTRACT:
Power dissipation of a CMOS circuit such as a microprocessor is reduced by dynamically slowing down the microprocessor clock during selected system operations such as hold, wait, or AT peripheral bus access cycles. The microprocessor clock is slowed to its minimum allowable frequency with precise synchronous control to maintain the accuracy of high frequency clock edges and to prevent glitches or substandard pulse widths.

REFERENCES:
patent: 4570219 (1986-02-01), Shibukawa et al.
patent: 4835681 (1989-05-01), Culley
patent: 4855615 (1989-08-01), Humpleman
patent: 4965524 (1990-10-01), Patchen
patent: 5155380 (1992-10-01), Hwang et al.

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