Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1998-03-05
2001-03-27
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S376000, C370S377000, C370S378000
Reexamination Certificate
active
06208641
ABSTRACT:
The present invention relates to a method in accordance with the preamble of the appended claim
1
and a switch in accordance with the preamble of the appended claim
5
for implementing switching with one bit resolution.
In digital transmission systems, data is transmitted in a successive stream of bits or symbols in time slots in which a predetermined number of bits, typically eight bits, are transmitted. In conventional PCM systems, these bits in one time slot are all reserved for one channel. In the European 2048 kbit/s basic multiplex system (in which the frame length is 32 time slots, i.e. 256 bits), altogether 30 speech channels each having a transmission rate of 64 kbit/s can be sent in this way. (The corresponding United States system has 24 channels, the rate being 1544 kbit/s).
Today, however, sophisticated speech encoding methods are available for improving the transmission capacity. The capacity of the above 2048 kbit/s basic system can be enlarged to 60 or 120 speech channels, for example. In such a case, the information in the speech channels has to be coded in a codec.
On account of such encoding methods, one speech channel thus only occupies some of the bits in the time slot, e.g. four or two bits out of eight. Codecs are also available wherewith a band of 7 kHz, for instance, can be transmitted by employing 6, 7 or 8 bits per time slot, i.e. by taking up 48, 56 or 64 kbit/s of the capacity of the basic multiplex system. Such approaches allow sub-channels, such as data channels, to be packed into one time slot, since less than 8 bits per time slot are needed to transmit the actual channel.
As a result of the development described above, a need has arisen to switch information to be transferred with one bit resolution instead of switching byte by byte (i.e. one word at a time). Such switches operating with one bit resolution have usually been implemented by using switching memory circuits having a width of one bit. The problem attending such an approach, however, is that the number of memory circuits increases quadratically in relation to the number of channels. Consequently, the memory circuits in practice pose a limitation on the capacity of the switch, since the physical size and also the power consumption of the switch rapidly increases to be impractically high when the number of channels increases.
This drawback also attends the switch disclosed in PCT application WO 93/16568. This publication discloses a switch switching on bit level and serving as an aid to a switch operating on byte level. In this switch, the switching has two phases in such a way that first the desired bytes are selected and thereafter the desired bits are selected from these bytes. The incoming bytes (words) to the auxiliary switch are first written into speech memories having a width of one byte, their number being equal to the number of bits in a byte. Under the control of a first control memory block, one byte is selected from each speech memory, and this byte is stored in a corresponding byte memory. Hence the number of byte memories is equal to the number of speech memories. Thereafter, under the-control of a second control memory block, one bit is selected from each byte memory for storage in a bit memory. In this way, a new PCM word is formed as the output of said switch.
The drawback attending the above solution is, however, still the fact that a relatively large number of memory circuits are needed, since the number of copies of each incoming byte must equal the number of bits in the byte. As a result, also the physical size and power consumption of the switch are still relatively high. Furthermore, this solution is intended to serve as a small auxiliary switch alongside a switch performing byte-oriented switching, and is not as such intended as an independent (high-capacity) switch.
It is an object of the present invention to provide an improvement in an independent switch with one bit resolution so as to afford considerably more efficient memory circuit utilization. This object is achieved with the method in accordance with the invention, which is characterized by what is disclosed in the characterizing portion of the appended claim
1
. The switch in accordance with the invention is characterized by what is disclosed in the characterizing portion of the appended claim
5
.
The idea of the invention is to implement a switch in the manner described hereinbelow. Input links of the switch are grouped to multiplexers which interleave the input signals of the switch into a smaller number of higher-rate serial signals. These signals are stored by writing the bits of the serial signals into the same memory location having a width of several bits. This is preferably carried out in such a way that bits corresponding to each other (i.e. bits occurring in the same write time slot) are stored at one memory location. In a preferred embodiment, a memory location corresponds in width to the number of multiplexers. Reading out from the memory is carried out in two steps, first selecting the correct byte from the memory and thereafter selecting the desired bit from this byte.
On account of the solution in accordance with the invention, it is possible to pack data very effectively into the memory of the switch. In other words, the switching memory can be implemented with a minimum of memory circuits, thus enabling low power consumption and a small physical size for the switch.
REFERENCES:
patent: 4718058 (1988-01-01), Van Vugt
patent: 5007049 (1991-04-01), Ohtsuka
patent: 5311517 (1994-05-01), Senoo
patent: 5317572 (1994-05-01), Satoh
patent: 5390184 (1995-02-01), Morris
patent: 5479398 (1995-12-01), Cyr
patent: 5841771 (1998-11-01), Irwin et al.
patent: 5862136 (1999-01-01), Irwin
patent: 5905735 (1999-05-01), Wille
patent: 6009078 (1999-12-01), Sato
patent: 418 475 (1991-03-01), None
patent: 483 516 (1992-05-01), None
patent: 93/1656 (1993-08-01), None
Kallioniemi Tapio
Ruuskanen Markku
Chin Wellington
Nokia Telecommunications Oy
Pham Brenda H.
Pillsbury & Winthrop LLP
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