Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
2003-07-11
2008-09-09
Sorrell, Eron J (Department: 2182)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C710S062000, C710S105000, C370S463000
Reexamination Certificate
active
07424552
ABSTRACT:
An enhanced switch
etwork adapter port (“SNAP™”) including collocated shared memory resources (“SNAPM™”) in a dual in-line memory module (“DIMM”) or any other memory module format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP® elements, common memory boards and the like.
REFERENCES:
patent: 4452700 (1984-06-01), Schneider et al.
patent: 4783730 (1988-11-01), Fischer
patent: 4972457 (1990-11-01), O'Sullivan
patent: 5230057 (1993-07-01), Shido et al.
patent: 5295246 (1994-03-01), Bischoff et al.
patent: 5592962 (1997-01-01), Hooberman
patent: 5673204 (1997-09-01), Klingelhofer
patent: 5889959 (1999-03-01), Whittaker et al.
patent: 5903771 (1999-05-01), Sgro et al.
patent: 5915104 (1999-06-01), Miller
patent: 5923682 (1999-07-01), Seyyedy
patent: 6026478 (2000-02-01), Dowling
patent: 6038431 (2000-03-01), Fukutani et al.
patent: 6047343 (2000-04-01), Olarig
patent: 6052134 (2000-04-01), Foster
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6076152 (2000-06-01), Huppenthal et al.
patent: 6108730 (2000-08-01), Dell et al.
patent: 6148355 (2000-11-01), Mahalingam
patent: 6192439 (2001-02-01), Grunewald et al.
patent: 6202111 (2001-03-01), Wallach et al.
patent: 6295571 (2001-09-01), Scardamalia et al.
patent: 6326973 (2001-12-01), Behrbaum et al.
patent: 6426879 (2002-07-01), Take
patent: 6452700 (2002-09-01), Mays, Jr.
patent: 6480014 (2002-11-01), Li et al.
patent: 6577621 (2003-06-01), Balachandran
patent: 6581157 (2003-06-01), Chiles et al.
patent: 6598199 (2003-07-01), Tetrick
patent: 6633945 (2003-10-01), Fu et al.
patent: 6799252 (2004-09-01), Bauman
patent: 6889959 (2005-05-01), Cholinski
patent: 59-206972 (1984-11-01), None
patent: 63-086079 (1988-04-01), None
PCI Technology Overview, Feb. 2003, Digi International, www.digi.com/pdf/prd—msc—pcitech.pdf, pp. 1-22.
FreeBSD Developers' Handbook Chapter 9, 1995, members.datafast.net.au/dft0802/specs/pcixpfaq.pdf, pp. 1-12.
Agarwal, A., et al., “The Raw Compiler Project”, pp. 1-12, http://gag-www.lcs.mit.edu/raw, Proceedings of the Sceond SUIF Compiler Workshop, Aug. 21-23, 1997.
Alabaharna, Osama, et al., “One the viability of FPGA-based integrated coprocessors”, ©1996 IEEE, Publ. No. 0-6188-7548-9/96, pp. 206-215.
Amerson, Rick, et al., “Teremac—Configurable Custom Computing”, ©1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 32-38.
Barthel, Dominique Aug. 25-26, 1997, “PVP a Parallel Video coProcessor”, Hot Chips IX, pp. 203-210.
Bertin, Patrice, et al., “Programmable active memories: a performance assessment”, ©1993 Massachusetts Institute of Technology, pp. 86-102.
Bittner, Ray, et al., “Computing kernels implemented with a wormhole RTR CCM”, ©1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 98-105.
Buell, D., et al. “Splash 2: FPGAs in Custon Computing Machine—Chapter 1—Custom Computing Machines: An Introdiction”, pp. 1-11, http://www.computer.org/espress/catalog/bp07413/spls-gh1.html (orginally believed published in J. of Supercomputing, vol. IX, 1995, pp. 219-230.
Casselman, Steven, “Virtual Computing and The Virtual Computer”, ©1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 43-48.
Chan, Pak, et al., “Architectural tradeoffs in field-programmable-device-based computing systems”, ©1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 152-161.
Clark, David, et al., “Supporting FPGA microporcessors through retargetable software tools”, ©1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 195-103.
Cuccaro, Steven, et al., “The CM-2X: a hybrid Cm-2/Xilink prototype”, ©1993 IEEE, Publ. No. 0/8186-3690-7/93, pp. 121-130.
Culbertson, W. Bruce, et al., “Exploting architectures for volume visualization on the Teramac custom computer”, ©1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 80-88.
Culbertson, W. Bruce, et al., “Defect tolerance on the Teramac custom computer”, ©1997 IEEE, Publ. 0-8186-8159-4/97, pp. 116-123.
Dehon, Andre, “DPGA-Coupled microprocessors: commodity IC for the 21stcentury”, ©1994 IEEEm Publ. No. 0-8186-5490-2/94, pp. 31-39.
Dehon, A., et al., “Matrix A Reconfigurable Computing Device with Configurable Instruction Distribution”, Hot Chips IX, Aug. 25-26, 1997, Stanford, Califonia, MIT Artificial Intelligence Laboratory.
Dhaussy, Philippe, et al., “Global control synthesis for an MIMD/FPGA machine”, ©1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 72-81.
Elliott, Duncan, et al., “Computational Ram: a memory-SIMD hybrid and its application to DSP”, ©1992 IEEE, Publ. No. 0-7803-0246-X/92, pp. 30.6.1-30.6.4.
Fortes, Jose, et al., “Systolic arrays, a survey of seven projects”, ©1987 IEEE, Publ. No. 0018-9162/87/0700-0091, pp. 91-103.
Gokhale, M., et al., “Processing in Memory: The Terasys Massively Parallel PIM Array” ©Apr. 1996, IEEE, pp. 23-31.
Gunther, Bernard, et al., “Assessing Socument Relevance with Run-Time Reconfigurable Machines”, ©1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 10-17.
Hagiware, Hiroshi, et al., “A dynamically microporgrammable computer with a low-level parallelisn”, ©1980 IEEE, Publ. No. 0018-9340/80/07000-0577, pp. 577-594.
Hartenstein, R. W., et al., “A General Approach in System Design Integrating Reconfigurable Accelerators,” http://xputers.informatik.uni-ki.de/paper/paper02B-1.html, IEEE 1996 Conference, Austin, TX, Oct. 9-11, 1996.
Hartenstein, Reiner, et al., “A reconfiguranvel data-driven ALU for Xputers”, ©1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 139-146.
Hauser, John, et al.: “GARP: a MIPS processor with a recongigurable co-processor”, ©1997 IEEE, Publ. No. 0-08186-8159-4/97, pp. 12-21.
Hyes, John, et al., “A microprocessor-based hypercube, supercomputer”, ©1986 IEEE, Publ. No. 0272-1732/86/1000-0006, pp. 6-17.
Herpel, H. -J., et al., “A Reconfigurable Computer for Embedded Control Applications”, ©1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 111-120.
Hogl, H., et al., “Enable++: A second generation FPGA processor”, ©1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 45-53.
King, William, et al., “Using MORRPH in an insustrial machine vision system”, ©1996.IEEE, Publ. NO. 08186-7548-9/96, pp. 18-26.
Manohar, Swaminathan, et al., “A pragmatic approach to systolic design”, ©1988 IEEE, Publ. No. CH2603-9/00/0000/0483, pp. 463-472.
Mauduit, Nicolas, et al., “Lneuro 1.0: a piece of hardware LEGO for building neural network systems,” ©1992 IEEE, Publ. No. 1045-9227/92, pp. 414-422.
Mirsky, Ethan A., “Coarse-Grain Reconfigurable Computing”, Massachusetts Institute of Technology, Jun. 1996.
Mirsky, Ethan, et al., “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resource”, ©1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 157-166.
Moley, Robert E. Jr., et al., “A Massively Parallel Syst
Hogan & Hartson LLP
Kubida William J.
Martensen Michael C.
Sorrell Eron J
SRC Computers, Inc.
LandOfFree
Switch/network adapter port incorporating shared memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Switch/network adapter port incorporating shared memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Switch/network adapter port incorporating shared memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3981715