Switch mode power stage

Details Switch mode power stage Switch mode power stage

2002-05-24

2004-02-17

Berhane, Adolf D. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S222000

Reexamination Certificate

active

06693411

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of power conversion devices and in particular, the invention provides an improved efficiency power stage.
BACKGROUND TO THE INVENTION
FIG. 1
illustrates a conventional boost/fly-back power stage
10
, which consists of a saw-tooth generator
11
, a pulse-width modulator
12
, feedback loop
13
, a switch
14
, an inductor
15
, a parasitic capacitance
16
, a rectifier
17
and a load
18
.
FIG. 2
illustrates operation of the power stage of
FIG. 1
in the discontinuous conduction mode. During time interval “A-B” switch
14
is ON and V
a
is substantially zero, causing current to ramp up in the inductor
15
. When the signal from the saw-tooth generator
11
exceeds a signal from the feedback loop
13
, the switch
14
is turned OFF (“B-C”). The current through the inductor then flows into the load
18
during time interval “C-D”, thus performing an energy transfer from the inductor
15
to the load
18
. The current in the inductor ramps down throughout the “C-D” interval depending on the value of load
18
. When the current in the inductor
15
reaches zero, a free oscillation begins (“D-E”). The frequency of this oscillation depends on the parasitic parameters of the switch (parasitic capacitance
16
) and the value of the inductor
15
. At time “E” determined by the generator
11
a new switching cycle begins (“E-A”).
When the circuit operates at a different power level, a relative position of the oscillating waveform “D-E” with respect to the beginning of a new cycle changes (A-B′-C′-D′-E′-A′). Therefore, with a different power level, switching can occur anywhere on the curve—at a maximum, (“E”), minimum (“E”) or anywhere in between.
Consequently this power stage has the problem that, when it is used in wide dynamic range applications, such as power factor correction (PFC) converters, it yields high harmonic distortion. The reasons for the high harmonic distortion are;
1. Variation of point “E” with respect to the voltage supply V
s
causes variation of power loss at the moment when the switch
14
is turned on. This is because the switching loss is high when the transition “E-A” is large, and the switching loss is low when the transition is small (“E-A”). As a result the power stage has high harmonic distortion in PFC applications.
2. Variation of point “E” with respect to V
3
causes variation of the control loop gain which degrades load regulation and also increases the harmonic distortion.
FIG. 3
illustrates another power stage topology
20
, called quasi-resonant turn-ON, which has more stable loop gain, lower harmonics and higher efficiency. (See
MC
34262
Power Factor Controllers semiconductor technical data, Motorola,
1996).
The power stage
20
consists of a one-shot pulse generator
21
, a pulse duration of which is controlled by the feedback
23
. The one-shot
21
is triggered by the comparator
22
with internal delay dT. Comparator
22
compares the voltage across the inductor
25
, Switch
24
, parasitic capacitance
26
, rectifier
27
and load
28
are of the standard topology.
FIG. 4
illustrates operation of the power stage
20
. During the time interval “F-G”, the one-shot
21
generates a pulse which closes the switch
24
, causing current in the inductor
25
to ramp up. The duration of the time interval “F-G” depends on the output of the feedback
23
which in turn depends on the error between the real load voltage V
L
and a target value. When the pulse generated by the one-shot
21
finishes, the switch
24
turns OFF, and the current in the inductor
25
passes into the load
27
during interval “H-I” and ramps down once again in a manner which depends on the value of load
28
. When the current in the inductor
25
becomes zero (“I”), self oscillation begins in the tank formed by the inductor
25
and the parasitic capacitance
26
. At point “J” the comparator
22
detects voltage polarity reversal across the inductor
25
. After the internal propagation delay of dT, ie at point “K”, the one-shot
21
is restarted, and the above described process repeats. By adjusting the delay dT to about one-quarter of the self-oscillation period of the inductor
25
and parasitic capacitance
26
it is possible to achieve switching at the bottom of the oscillating waveform thus maximising efficiency.
Due to the fact that point “K” is always below supply voltage V
s
, circuit
20
has an advantage over circuit
10
of
FIG. 1
in that the loop gain is not subject to fluctuations, resulting in lower harmonics.
However power stage
26
does have a disadvantage in that it has low efficiency at low power level.
This is because at low power level, the duration of both the primary conduction time (“L-M”) and the secondary conduction time (“N-O”) is small, as shown in FIG.
5
. This results in shrinking of the switching period down to perhaps half of the self-oscillation period. As a result the switching frequency undesirably increases, resulting in high switching loss. Attempts to reduce the parasitic capacitance
26
would not help increase efficiency because the switching frequency would increase even more. Therefore, there exists a need for a power stage which minimises switching losses and possesses high efficiency both at high power levels and at low power levels.
Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is solely for the purpose of providing a context for the present invention. It is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present invention as it existed before the priority date of each claim of this application.
Throughout this specification the word “comprise”, or variations such as “comprises” or “comprising”, will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.
SUMMARY OF THE INVENTION
According to a first aspect, the present invention provides a power conversion device operable in a discontinuous conduction mode under the control of a switching means and wherein during operation in the discontinuous conduction mode, an oscillating voltage exists across the switching means prior to a turn-on of the switching means, the device comprising:
switch control means arranged to cause turn-on of the switching means to occur at a minimum of the oscillating voltage; and
timing means arranged to provide a controlled time period following a first turn-on of the switching means, during which a second turn-on of the switching means can not occur.
The power conversion device of the first aspect of the present invention is advantageous in that a low power level of operation of the device and a short conduction time of the switching means does not lead to an undesirable increase in switching frequency. Consequently, a reduction in a parasitic capacitance of the switch will be rewarded by an increase in efficiency.
Furthermore the present invention is of particular importance in high efficiency applications, where an increase in efficiency of even a fraction of a percent is of importance.
Preferably, the timing means comprises
a gate which, when open, prevents a turn-on signal from reaching the switching means, or, alternatively prevents generation of a turn-on signal; and
a timer which is reset at each turn-on of the switching means, and holds the gate open for the controlled time period following each reset.
The switch control means preferably comprises:
a comparator arranged to compare the oscillating voltage to a reference voltage about which the oscillating voltage oscillates, and to produce an output logic signal corresponding to the polarity of the oscillating voltage with respect to the reference voltage;
delay means arranged to delay the output logic signal by one quarter of a period of oscil

Affiliated with

Also associated with

Rating

Switch mode power stage does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Switch mode power stage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Switch mode power stage will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3319268