Switch matrix among tributaries of a telecommunication...

Details Switch matrix among tributaries of a telecommunication... Switch matrix among tributaries of a telecommunication...

1999-06-15

2004-01-06

Nguyen, Chau (Department: 2663)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C365S189120

Reexamination Certificate

active

06674752

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a switch matrix among tributaries of a telecommunication network, specifically a telecommunication network operating on flows of data which are structured according to SDH protocol, said switch matrix comprising a set of parallel branches, with each branch comprising at least a first space stage able to select and pack from the input data flow a subset of data to be exchanged, a second time stage able to store the data subset to be exchanged and comprising a random access memory device, associated with a write memory and a read memory, said write memory and read memory being driven by a microprocessor and a master counter. Hereafter, the term “telecommunication networks” will mean synchronous signal carrying networks, specifically according to SDH (Synchronous Digital Hierarchy) standard.
BACKGROUND ART
Telecommunication networks are equipped with elements located in the switching stations, called “switch matrixes”, which can carry out connections between communication circuits, the so-called ‘tributaries’, with the aim of putting users in communication. Switch matrixes operate according to users' requests or under direct control of the network manager, establishing the so-called semi-permanent connections.
As known, SDH frames, e.g. frames STM-1 generally consist of a subframe set called Virtual Containers, which in turn consist of lower order Virtual Containers according to a hierarchic structure. Therefore, an SDH frame will appear like a subframe time sequence and a switch matrix fulfills its function of connection maker by reassigning the location of Virtual Containers within the SDH frame.
The most common manner for obtaining a switch matrix consists in employing a random access memory element, i.e. a RAM memory, equipped with two access ports or gates, i.e. at least a write port and a read port. RAM memories are known, for instance, having 16 write ports and 8 read ports. Such a RAM memory is able to exchange all Virtual Containers contained in the input frames and generate 8 output frames. Moreover, it is a strictly nonblocking structure, i.e. always able to establish connections without altering other connections already established. On the other hand, a RAM memory requires that during write operations a proper counter will sequentially supply the addresses where to write input data in the memory element. A read control memory containing read addresses, i.e. the data read order is also needed to rearrange output frames to obtain desired connections.
However, even if the use of a RAM memory according to the above mode is advantageous for its simple implementation, considerable drawbacks exist since RAM memories of the type described above are not conventional memories, i.e. they need a design strictly associated with the type of switch matrix to be obtained.
The use of a switch matrix of a so-called “knock-out switch” type is known. This is a multistage connection type, where the main modular element consists of a space-time-space matrix. The “knock-out switch” allows for employing a memory so sized as to store the data exclusively related to reassignment.
The purpose of the first space stage is to adapt the input data flow to obtain a sequential filling of a elastic memory, which represents the subsequent time stage.
The second stage, i.e. the so-called subsequent time stage, operates the exchange of the time position of the tributaries which have been sequentially randomly introduced in the output frame. It consists of a sequential write/programmable read-memory.
The third stage, if required, detects the data to be routed to several outputs when the second stage has an output capacity greater than a frame.
FIG. 1
shows a block diagram of a “knock-out switch” KS according to the known state of the art.
As it can be noted an input data flow DIN containing an integer number N of frames ST is available. Each frame ST is divided internally in time units TS, identifying the various bytes to be switched. In the following description the number N will be equal to 8, unless otherwise indicated. Input data flow DIN is sent to a number m of branches BR
1
...BR
m
in parallel. The same structure is duplicated on each of said branches BR
1
...BP
m
, said structure comprising a concentrator rotator block CR controlled by a write control memory WCM through a write sequence WW. Said write sequence WW contains information where active bytes are located, i.e. the pertaining bytes DSC for the exchange. A buffer BUF, namely a temporary transit memory is provided downstream the concentrator rotator block CR. Then a memory DTRAM driven by a read control memory RCM will follow through a read word RR, which contains the addresses to be read in the memory DTRAM. Said memory DTRAM which is an elastic multiport RAM memory is provided with a plurality of outputs OUT. Said outputs OUT are N/m for each memory DTRAM, so that the memory DTRAM
1
will have OUT
0
to OUT
N/m−1
outputs and memory DTRAM
m
OUT
N(m−1)/m
to OUT
N−1
outputs. Thus, in the knock-out switch KS what represented a single memory matrix is divided in m branches BR
1
...BR
m
. Each of said branches BR1...BRm only elaborates sets of time units or subframes ST relating to a group of N/m outputs OUT. This will obviously allow the use of smaller memories DTRAM as a function of the number m of branches BR
1
...BR
m
being chosen.
The concentrator rotator block CR is substantially a combinatorial network with N inputs and outputs. The concentrator rotator block CR has to select the bytes DSC relating to its branch BR in the data flow DIN, place them in adjacent positions and then rotate the thus obtained set of bytes to completely fill the memory DTRAM.
FIG. 2
shows operation of a concentrator rotator block CR with N=5, in six subsequent time units TS. Pertaining bytes DSC spread at the input of the concentrator rotator block CR are concentrated and properly placed inside the memory DTRAM through a circular shift operation, i.e. a rotation. Naturally, during these operations the concentrator rotator block CR is driven by the write sequence WW.
The subsequent buffer BUF is required should the memory DTRAM only allow to write words of a predetermined length. Since the number of output bytes from the concentrator rotator block CR is variable in time, the bytes are temporary stored in the buffer BUF till a full word is formed. As soon as this happens, the word obtained is transferred to the memory DTRAM.
The concentrator rotator block CR is driven by the write control memory WCM, which is a memory whose depth is equal to the number of time units TS forming the frame ST and a word length equal to the one of the write sequence WW of N bits. Being said j and k generally two integer indexes, the j-th bit of the k-th write sequence WW in the write control memory WCM is set at 1 if the byte in the k-th time unit TS of the j-th input frame ST has to be saved in the memory DTRAM belonging to the same branch of the write control memory WCM under consideration.
When the memory DTRAM is completely filled, it is read with random access, according to the contents of the read control memory RCM.
Also the “knock-out switch” has some drawbacks, even if it allows subdivision of the memory in a plurality of smaller memories.
When using a RAM standard memory, each byte corresponding to a Virtual Container is always stored in the same memory location. This does not occur for the knock-out switch, due to concentration and rotation operations. Therefore, if a connection should be changed, the content of the whole read control memory has to be refreshed, whereas for the write control memory only bit related to the modified connection needs to be changed. Therefore an external microprocessor to refresh control memories is used. The refreshing step of control memories is quite crucial, since during the change of the write control memory content, it may happen that in the memory the position of some bytes not involved by the new connection will change. Substantially, this happens

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