Switch logic for shift register latch pair

Details Switch logic for shift register latch pair Switch logic for shift register latch pair

1982-11-30

1985-08-13

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

307272R, G11C 1900

Patent

active

045354677

ABSTRACT:
A Level Sensitive Scan Design (LSSD) Shift Register Latch pair implemented in current switch logic is disclosed. The arrangement is characterized by the logic used to control the L1 and L2 latches being implemented in Differential Cascode Current Switch logic and the L1/L2 latches being coupled to only one current source. A "merged" L1/L2 latch arrangement employing only one current source is provided for an LSSD testing environment.

REFERENCES:
patent: 3294919 (1966-12-01), Kerr et al.
patent: 3443238 (1969-05-01), Flynn et al.
patent: 3618033 (1971-11-01), Nordquist et al.
patent: 3953746 (1976-04-01), Fett
patent: 4168540 (1979-09-01), Delker et al.

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