Switch-level timing simulation based on two-connected components

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364488, 364490, 364578, G06F 1520

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active

053052293

ABSTRACT:
A method for simulating a transistor circuit determines which nodes in the circuit change state in response to events, and then accurately computes the times at which those nodes change states. Using parasitic capacitance and transistor conductance values extracted from the circuit layout, this method and evaluates driving-point resistances and delays in an RC-network representation of the complete circuit.

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