Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-03-23
2002-06-18
Frejd, Russell (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000, C716S030000
Reexamination Certificate
active
06408264
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to simulation of electronic circuits and, more particularly, to switch level simulation.
BACKGROUND INFORMATION
Switch level simulation is commonly used to model the operation of a digital circuit. Typically, each transistor in the digital circuit is modeled with a switch having a conduction path with a delay property. In addition, switch level simulation may also include a strength parameter corresponding to the conductances of the various transistors. Other types of simulation can be used, such as analog simulation (e.g., spice). Switch level simulation generally can be performed much faster than analog modeling (especially for relatively large circuits), while still maintaining accuracy in verifying the logic functionality of the circuit design.
However, one problem with switch level simulation is in modeling circuits with cross-coupled devices. Cross-coupled devices (e.g. sense amplifiers) are commonly used in digital memory circuits, such as DRAMs and SRAMs. Cross-coupled devices have a metastable state that is difficult to model using conventional switch level simulation techniques. In particular, the voltages at complementary nodes of a cross-coupled device may be unknown during operation, which, without accounting for the metastable state, can lead to failure in the modeling. Another difficulty is that cross-coupled devices are sensitive to voltage level changes that may not result in changes in logic level, which are difficult to model using switch level techniques.
One conventional solution to this problem is to use strength allocation techniques in which a cross-coupled device that is “downstream” from another cross-coupled device in a data path is allocated a weaker strength than the upstream cross-coupled device. These techniques allow the upstream cross-coupled device to overwrite the downstream cross-coupled device, causing data to ripple downstream. However, these strength allocation techniques fail when the datapath is bidirectional. In addition, these techniques may not be practical when the datapath contains many stages of cross-coupled devices.
Another conventional solution is to remove all of the cross-coupled devices from the circuit and replace each cross-coupled device with an appropriate “black box”. The black box is a behavioral model of the cross-coupled device being replaced. The designer must construct a behavioral model for each cross-coupled device and its associated control circuitry. Because of the complexity of the behavior of cross-coupled devices, constructing these black boxes consumes valuable engineering resources. In addition, the switch level simulation in effect verifies the functionality of the black boxes rather than of the actual cross-coupled devices in the circuit, thereby throwing the accuracy of the entire model into question.
Therefore, what is needed is a technique for modeling cross-coupled devices in a switch level simulation tool that more closely relies on the actual devices in the cross-coupled devices, reduces the consumption of engineering resources, and maintains or improves modeling accuracy relative to conventional techniques.
SUMMARY
In accordance with the present invention, a switch level simulation system having a netlister, a cross-coupled device detector, a cross-coupled device transformer and a switch level simulator is provided. The user provides a circuit design to the netlister, which then generates a netlist of the circuit. The cross-coupled device detector searches the netlist to find all of the cross-coupled devices in the circuit design. In one aspect of the present invention, the cross-coupled device detector also determines whether the cross-coupled device has a “rail” node directly connected an external voltage source line (e.g., VDD or VSS) without an “enable” device (i.e., cross-coupled devices may be enabled by activating a pull-up or pull-down device to complete the differential current paths in the cross-coupled devices). Such a cross-coupled device is referred to herein as a Type B cross-coupled device. The cross-coupled device transformer transforms each Type B cross-coupled device into a transformed cross-coupled device. In one aspect of the present invention, the cross-coupled device transformer inserts a device at the rail node mirroring the enable device. For example, if the Type B cross-coupled device is enabled by activating an N-channel pull-down transistor (which means the rail node is connected to the VDD line), the cross-coupled device transformer inserts an N-channel transistor between the VDD line and the rail node. The mirror device allows the transformed cross-coupled device to provide a high impedance state to emulate the meta-stable state of the cross-coupled device during switch level simulation, thereby maintaining and even improving the accuracy of the simulation. The simple insertion of the mirror device significantly reduces the engineering resources needed to model cross-coupled devices compared to the aforementioned conventional techniques while maintaining a close resemblance to the actual cross-coupled device.
REFERENCES:
patent: 4907180 (1990-03-01), Smith
patent: 5051941 (1991-09-01), Takamine et al.
patent: 5278769 (1994-01-01), Bair et al.
patent: 5297066 (1994-03-01), Mayes
patent: 5305229 (1994-04-01), Dhar
patent: 5553008 (1996-09-01), Huang et al.
patent: 5701254 (1997-12-01), Tani
patent: 5703798 (1997-12-01), Dhar
patent: 5822567 (1998-10-01), Takeuchi
patent: 6190433 (2001-02-01), Van Fleet et al.
patent: 6311146 (2001-10-01), Hao et al.
Santarini, “Avant! Rolls Event-Driven Timing Tool for Milkyway”, Electronic Engineering Times, Issue 988, p. 79 (Jan. 1998).*
Xirgo et al, “Digital MOS Circuit Partitioning with Symbolic Modeling”, IEEE Proceedings of the Design, Automation and Test in Europe Conference, pp. 503-508 (Mar. 1999).
Chen Lidong
Kirsch Howard C.
Su Jason Tzu-Jung
Broda Samuel
Frejd Russell
Vanguard International Semiconductor-America
LandOfFree
Switch level simulation with cross-coupled devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Switch level simulation with cross-coupled devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Switch level simulation with cross-coupled devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2971006