Switch level simulation employing dynamic short-circuit ratio

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G06F 9455

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057037981

ABSTRACT:
A switch level simulator having switch level speeds with near the accuracy of a circuit level simulator. Circuit parameters such as peak current, delay, and charge are calculated by using a dynamic short-circuit ratio. In the preferred embodiment a computer having a processor and memory is used to run the circuit simulations. A lookup table is built which represents how the circuit parameters vary with a change in the dynamic short-circuit ratio. The dynamic short-circuit ratio is calculated by taking the ratio of a first resistance in a first circuit path switching OFF to a second resistance in a second circuit path switching on. The circuit paths might be a parallel or series set of transistors which need to be combined to form an effective resistance for each path. The calculated dynamic short-circuit ratio is then used in the lookup table to determine the parameters in question.

REFERENCES:
patent: 4815024 (1989-03-01), Lewis
patent: 4817012 (1989-03-01), Cali'
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 4835726 (1989-05-01), Lewis
patent: 4907180 (1990-03-01), Smith
patent: 4967367 (1990-10-01), Piednoir
patent: 5051911 (1991-09-01), Kimura et al.
patent: 5095454 (1992-03-01), Huang
patent: 5163016 (1992-11-01), Har'El et al.
patent: 5202841 (1993-04-01), Tani
patent: 5278769 (1994-01-01), Bair et al.
patent: 5305229 (1994-04-01), Dhar
patent: 5446676 (1995-08-01), Huang et al.
patent: 5477460 (1995-12-01), Vakirtzis et al.
patent: 5515291 (1996-05-01), Omori et al.
patent: 5553008 (1996-09-01), Huang et al.
patent: 5572437 (1996-11-01), Rostoker et al.
"Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits," Harry J.M. Veendrick, IEEE Journal of Solid-State Circuits, vol. SC-19, No. 4, Aug. 1984, pp. 468-473.
"Hercules: A Power Analyzer for MOS VLSI Circuits," Akhilesh Tyagi, 1987 IEEE, pp. 530-533.
"Inverter Models of CMOS Gates for Supply Current and Delay Evaluation," A. Nabavi-Lishi, et al. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 10, Oct. 1994, pp. 1271-1279.
"Input Waveform Slope Effects in CMOS Delays," IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1588-1590.
"Timing Simulation for Large Digital MOS Circuits," Advances in Computer-Aided Engineering Design, 1986, vol. 1, pp. 1-92.
"Delay Modeling and Timing of Bipolar Digital Circuits," D. G. Saab, et al., 25th ACM/IEEE Design Automation Conference, Paper 21.2, pp. 288-293.
"Computing Signal Delay in General RC Networks by Tree/Link Partitioning," Pak K. Chan, et al., 26th ACM/IEEE Design Automation Conference, Paper 31.1, pp. 485-490.
"A Recursive Technique for Computing Delays in Series-Parallel MOS Transistor Circuits," Jean-Paul Caisso, et al., IEEE Transactions on Computer-Aided Design, vol. 10, No. 5, May 1991, pp. 589-595.
"Signal Delay in RC Tree Networks," Jorge Rubinstein, et al., IEEE Transactions on Computer-Aided Design, vol. CAD-2, Jul. 1983, pp. 202-211.
"The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers," W. C. Elmore, Journal of Applied Physics, vol. 19, Jan., 1948, pp. 55-63.
"Signal Delay in General RC Networks," Tzu-Mu Lin, et al., IEEE Transactions on Computer-Aided Design, vol. CAD-3, No. 4, Oct. 1984, pp. 331-349.
"Depth-First Search and Linear Graph Algorithms," Robert Tarjan, SIAM J. Comput., vol. 1, No. 2, Jun. 1972, pp. 146-160.
"A Switch-Level Model and Simulator for MOS Digital Systems," Randal E. Bryant, IEEE Transactions on Computers, vol. C-33, No. 2, Feb. 1984, pp. 160-177.
"Automatic Modeling of Switch-Level Networks Using Partial Orders," Prathima Agrawal, et al., IEEE Transactions on Computer-Aided Design, vol. 9, No. 7, Jul. 1990, pp. 696-707.
"Magnitude Classes in Switch-Level Modeling," E. Cemy, et al., IEEE 1988, pp. 284-288.
"Switch-Level Simulation Using Dynamic Graph Algorithms," Dan Adler, IEEE 1991, pp. 346-355.
"Leadout: A Static Timing Analyzer for MOS Circuits," G. Szymanski, IEEE International Conference on Computer-Aided Design, 1986, Santa Clara, CA, pp. 130-133.
Principles of CMOS VLSI Design, N. Weste, et al., 1985, Addison-Wesley, Reading, Mass., pp. 317-319.
Introduction to Electric Circuits, H.W. Jackson, 1981, Prentice-Hall, Inglewood Cliffs, NJ, pp. 448-450.
"Dividing a Graph Into Triconnected Components," J.E. Hopcroft, et al., SIAM Journal on Computing, Sep. 1973, vol. 2, No. 3, pp. 135-158.
Data Structures and Network Algorithms, R.E. Tarjan, Society for Industrial and Applied Mathematics, 1983, Philadelphia, PA, pp. 85-96.
"A Switch-Level Timing Verifier for Digital MOS VLSI," J. K. Ousterhout, IEEE Transactions on CAD, Jul. 1985.
"Delay Prediction from Resistance-Capacitance Models of General MOS Circuits," D. Martin, et al., IEEE Transactions on CAD, Jul. 1993, vol. 12, No. 7.
Tjarnstrom, Power Dissipation Estimate by Switch Level Simulation, IEEE, pp. 881-884, May 1989.
Rouatbi et al, Power Estimation Tool for Sub-Micron CMOS VLSI Circuits, IEEE, pp. 204-209, Nov. 1992.
Ruan et al, Logic Simulation with Current-Limited Switches, IEEE, pp. 133-141, Feb. 1990.

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