Coded data generation or conversion – Analog to or from digital conversion – With particular solid state devices
Reexamination Certificate
2000-08-08
2002-01-22
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
With particular solid state devices
C341S144000, C341S133000, C341S153000, C341S136000, C341S118000, C341S155000, C341S154000, C341S119000, C341S172000, C327S303000, C327S051000, C327S563000, C327S091000
Reexamination Certificate
active
06340939
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to switch driver circuitry for use, for example, in digital-to-analog converters.
2. Description of the Related Art
FIG. 1
of the accompanying drawings shows parts of a previously-considered current-switched digital-to-analog converter (DAC)
1
. The DAC
1
is designed to convert an n-bit digital input word into a corresponding analog output signal.
The DAC
1
includes a plurality of individual binary-weighted current sources
2
1
to
2
n
corresponding respectively to the n bits of the digital input word applied to the DAC. Each current source passes a substantially constant current, the current values passed by the different current sources being binary-weighted such that the current source
2
1
corresponding to a least-significant-bit of the digital input word passes a current I, the current source
2
2
corresponding to the next-least-significant-bit of the digital input word passes a current
2
I, and so on for each successive current source of the converter.
The DAC
1
further includes a plurality of differential switching circuits
4
1
to
4
n
corresponding respectively to the n current sources
2
1
to
2
n
. Each differential switching circuit
4
is connected to its corresponding current source
2
and switches the current produced by the current source either to a first terminal connected to a first connection line A of the converter or a second terminal connected to a second connection line B of the converter. The differential switching circuit receives one bit of the digital input word (for example the differential switching circuit
4
1
receives the least-significant-bit of the input word) and selects either its first terminal or its second terminal in accordance with the value of the bit concerned. A first output current I
A
of the DAC is the sum of the respective currents delivered to the differential-switching-circuit first terminals, and a second output current I
B
of the DAC is the sum of the respective currents delivered to the differential-switching-circuit second terminals. The analog output signal is the voltage difference V
A
-V
B
between a voltage V
A
produced by sinking the first output current I
A
of the DAC
1
into a resistance R and a voltage V
B
produced by sinking the second output current I
B
of the converter into another resistance R.
FIG. 2
shows a previously-considered form of differential switching circuit suitable for use in a digital-to-analog-converter such as the
FIG. 1
converter.
This differential switching circuit
4
comprises first and second PMOS field effect transistors (FETs) S
1
and S
2
. The respective sources of the transistors S
1
and S
2
are connected to a common node TAIL to which a corresponding current source (
2
1
to
2
n
in
FIG. 1
) is connected. The respective drains of the transistors S
1
and S
2
are connected to respective first and second output nodes OUTA and OUTB of the circuit which correspond respectively to the first and second terminals of each of the
FIG. 1
differential switching circuits.
Each transistor S
1
and S
2
has a corresponding driver circuit
6
1
or
6
2
connected to its gate. Complementary input signals IN and INB are applied respectively to the inputs of the driver circuits
6
1
and
6
2
. Each driver circuit buffers and inverts its received input signal IN or INB to produce a switching signal SW
1
or SW
2
for its associated transistor S
1
or S
2
such that, in the steady-state condition, one of the transistors S
1
and S
2
is on and the other is off. For example, as indicated in
FIG. 2
itself, when the input signal IN has the high level (H) and the input signal INB has the low level (L), the switching signal SW
1
(gate drive voltage) for the transistor S
1
is at the low level L, causing that transistor to be ON, whereas the switching signal SW
2
(gate drive voltage) for the transistor S
2
is at the high level H, causing that transistor to be OFF. Thus, in this condition, all of the input current flowing into the common node TAIL is passed to the output node OUTA and no current passes to the output node OUTB.
When it is desired to change the state of the circuit
4
of
FIG. 2
so that the transistor S
1
is OFF and the transistor S
2
is ON, complementary changes are made simultaneously in the input signals IN and INB such that the input signal IN changes from H to L at the same time as the input signal INB changes from L to H. As a result of these complementary changes, it is expected that the transistors S
1
and S
2
will switch symmetrically, that is that the transistor S
1
will turn OFF at exactly the same moment that the transistor S
2
turns ON. However, in practice there is inevitably some asymmetry in the turn-ON and turn-OFF speeds. This can result in a momentary glitch at the common node TAIL which may in turn cause glitches at one or both output nodes of the circuit, producing a momentary error in the DAC analog output value until all of the switches have switched completely. These glitches in the analog output signal may be code-dependent and result in harmonic distortion or even non-harmonic spurs in the output spectrum.
As the size of the glitch associated with the switching of the differential switching circuit is dependent on the symmetry of the complementary changes in the input signals IN and INB, much attention has been directed to generating and delivering these input signals to the differential switching circuit synchronously with one another. However, it is found in practice that, even if the input signals are perfectly symmetrical, the drive circuits
6
1
and
6
2
which derive the switching signals from the input signals inevitably introduce asymmetry into the switching signals SW
1
and SW
2
which actually control the transistors S
1
and S
2
. Such asymmetry results in transient output current distortion in any individual differential switch circuit. Furthermore, in a DAC employing multiple differential switch circuits, it also results in a variation between the switching times of the different circuits. These variations lower the spurious-free dynamic range (SFDR) of the DAC (a measure of the difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth). These variations also lead to code-dependency of the analog output signal of the converter.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided switch driver circuitry comprising: first and second output nodes; a current-voltage converter connected to said first and second output nodes to provide a current path through which current is permitted to flow in a first direction from said first to said second output node, or in a second direction from said second to said first output node, when the circuitry is in use, for producing a potential difference between said first and second output nodes that is dependent upon the magnitude and direction of the current flow; and switching circuitry connected with said first and second output nodes and switchable, in dependence upon an applied control signal, from a first state, in which a current of preselected magnitude is caused to flow in said first direction through said current path, to a second state in which a current of substantially the same magnitude as said preselected magnitude is caused to flow in said second direction through said current path, a current-voltage characteristic of the current-voltage converter being such that said potential differences produced respectively in said first and second states have substantially the same magnitudes but opposite polarities.
Such switch driver circuitry can provide improved symmetry of operation.
According to a second aspect of the present invention there is provided a switch circuit comprising: first and second output nodes; a current-voltage converter connected to said first and second output nodes to provide a current path through which current is permitted to flow in a first direction f
Fujitsu Limited
Mai Lam T.
Tokar Michael
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