Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-06-24
2004-04-13
Pham, Chi (Department: 2667)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S415000
Reexamination Certificate
active
06721324
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an ATM switching system, which exchanges an ATM cell between specific input port, and output port based on ATM (Asynchronous Transfer Mode) technology. More specifically, the invention relates to the switch control technique in an input buffer type switch.
FIG. 26
indicates a block diagram showing an example of the configuration of a conventional ATM switching system. Referring to
FIG. 26
, the conventional ATM switching system comprises a crossbar type switch section
20
which exchanges an ATM cell (hereinafter called a cell), input buffer sections
10
-
1
to
10
-n which store the cell arrived at input ports (input buffer sections
10
-
3
to
10
-n are not shown) and an arbiter section
2
. The switch exchange
22
of the crossbar type switch section
20
closes (turns on) the cross point
22
-
2
of grid-like transmission lines, thereby exchanging a cell between specific input highway
23
and output highway
24
. If two or more input ports
100
-
1
to
100
-n send a cell to a specific output port
101
-
1
to
101
-n, collision will occur between the cells and the cell data is broken. Therefore, the number of input ports to send a cell to a specific output port must be limited to only one.
The input buffer sections
10
-
1
to
10
-n provided for each input port and each output port has one FIFO (First In First Out) logic queue
1
. Cells arrived at the input port of
100
-
1
to
100
-n are stored at the end of the FIFO logic queue
1
, and the cells stored on the FIFO logic queue
1
are sequentially sent to the input highway
23
.
The input buffer sections
10
-
1
to
10
-n send a connection request signal
30
holding information about the output ports
101
-
1
to
101
-n to which a cell is transferred to the arbiter section
2
.
The arbiter section
2
determines the cross point
22
-
2
of the switch exchange
22
at which the switch is closed based on the connection request signal
30
to prevent collision between cells. The arbiter section
2
generates a competition arbitration signal
31
which notifies the arbitration result to the input buffer sections
10
-
1
to
10
-n.
Operation of the conventional ATM switching system shown in
FIG. 26
is explained. Cells arrived at the input port
100
-
1
to
100
-n are stored at the end of the FIFO logic queue
1
. The input ports
100
-
1
to
100
-n detect the destination output ports
101
-
1
to
101
-n based on the header information held by the first cell in the FIFO logic queue, and requests the arbiter section
2
to connect to the destination output port.
After integrating the connection request signal
30
from the input buffer sections
10
-
1
to
10
-n, when two or more input ports
100
-
1
to
100
-n request connection to one of the output ports
101
-
1
to
101
-n, namely when competition for one destination occurs, the arbiter section
2
arbitrates the competition and gives the arbiter section
2
the connection right to only one output port.
The arbiter section
2
gives the connection right to any output port that receives the connection request from only one input port.
After arbitration for all output ports, the arbiter section notifies the input buffer sections
10
-
1
to
10
-n of success or failure of the request using a competition arbitration signal
31
.
The input buffers
10
-
1
to
10
-n whose request is succeeded sends the first cell to the input highway
23
. Based on the arbitration result from the arbiter section
2
, the switch exchange
22
closes the specified cross point
22
-
2
and transfers said first cell to the specified output highway
24
.
Problems with the above-mentioned conventional ATM switching system are described.
FIG. 27
shows the exemplary operation of the conventional ATM switching system in FIG.
26
.
FIG. 27
depicts the state that the first cell at the input port #
1
obtains the connection right to the output port #
3
and the cross point of the switch exchanger
22
(shown in hatched square) is closed. The first cells at other input ports #
2
, #
3
and #
4
request connection to the output port #
3
but do not gain the connection right, and they are in the not-transferred state.
At this time, for the cell stored next to the first cell at other input port (the first cell requesting connection to the output port #
3
), though the input highway
23
is not used and the destination output highway is also idle, transfer is impossible because the first cell is closed. Such state of cell is called “HOL (Head Of Line) blocking” which causes throughput decrease or cell loss.
Even with the configuration in which logic queues equivalent to output ports are provided in the input buffer section and input cells are stored separately for the logic queues corresponding to the destination output obtained from the cell header information, the connection request signal
30
from the input buffer section can convey the connection request to only one output port, and if that connection request is rejected, throughput will be decreased.
Moreover, in the prior art, as a logic queue to send a cell is selected in the input buffer section, regardless of whether the logic queue which issued the connection request last time gains the connection right or not, the logic queues are periodically checked for storage of cells sequentially from the queue positioned next to the queue which issued the connection request last time, and the queue storing the cell searched first is selected.
In this conventional selection system, the logic queues selected in all input buffers are apt to request the same output port as a destination, and competition occurs frequently and throughput is restricted.
Further, as the port speed increases, the time to send a cell is absolutely reduced, and arbitration for the cell to be sent next must be completed within this reduced time, and the arbiter section has to use a large capacity high speed processor.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems, the objective of the present invention is to provide a switch control system in an input buffer type ATM switching system which prevents occurrence of blocking, improves throughput and reduces cell loss.
Furthermore, the objective of the present invention is to provide a switch control system which enables a small capacity processor to perform candidate selection to determine from which input buffer the connection right is issued to which output port, and competition arbitration to determine to which input port the connection right is given when competition occurs for one output port.
The object of the present invention is achieved by the switch control system of ATM switching system which exchanges an ATM cell between an input port and an output port; the input buffer type ATM switching system comprising an input buffer section installed for each input port, an arbiter section to determine to which input port the connection right is given, or which the cross point of a crossbar type switch is to be turned on/off, and a crossbar type switch to exchange an ATM(asynchronous transfer mode) cell between an input port and an output port; wherein the logic queue located next to the queue which gained the output port connection right last time is taken as a start point of rotation priority control which checks whether a logic queue holds cells in the predetermined order, and selects the logic queue holding the cell searched first, in the candidate selection process to select the logic queue issuing the connection request to a certain output port out of a plurality of logic queues provided in said input buffer section to store input cells for each output port or each connection, when determining the logic queue in said input buffer section from which a cell is transferred. Further, in the switch control system of the ATM switching system of the present invention, the input port positioned next to the input port which gained the output port connection right last time is taken as a start point of said rotatio
Boakye Alexander O.
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Corporation
Pham Chi
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