Switch components and multiple data rate non-blocking switch net

Details Switch components and multiple data rate non-blocking switch net Switch components and multiple data rate non-blocking switch net

1988-12-09

1990-04-03

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

34082579, 34082503, 370 581, 379272, H04Q 342

Patent

active

049144294

ABSTRACT:
A switching component preferably in integrated circuit form is provided. The switching component has a plurality of inlet and outlet data ports with associated inlet and outlet clock ports, a clock regenerator and a flip-flop for each outlet data port, and a switch matrix for coupling each inlet data port and its associated inlet clock port to any outlet data port and its associated outlet clock port. The clock regeneration means obtains the clock signal exiting the switching core and regenerates the clock signal waveshape. The flip-flop causes data exiting the switching core to be clocked out of the switching component synchronously with its associated regenerated clock signal according to the regenerated clock signal. A plurality of identical switching components can be arranged in a folded Clos arrangement having a plurality of stages to provide a desired switch network of any size. The use of multiple stages is permitted as the clock regeneration means associated with each port prevents signal dispersion and signal clock skew. The passing and switching of clock signals along with the data also permits the switching matrix to simultaneosuly handle lines having different rates, provided that a line of a given rate which is an input to the switching network must be connected to another line of the same rate which is an output of the switching network.

REFERENCES:
patent: 4613969 (1986-09-01), Draayer
patent: 4667320 (1987-05-01), Onno et al.
patent: 4763123 (1988-08-01), Yasuda
patent: 4807280 (1989-02-01), Posner et al.

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