Switch-body PMOS switch with switch-body dummies

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

Reexamination Certificate

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Details

C327S091000

Reexamination Certificate

active

07969203

ABSTRACT:
An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.

REFERENCES:
patent: 4308468 (1981-12-01), Olson
patent: 5019731 (1991-05-01), Kobayashi
patent: 5111072 (1992-05-01), Seidel
patent: 6265911 (2001-07-01), Nairn
patent: 7015729 (2006-03-01), Tursi et al.
patent: 7119585 (2006-10-01), Ranganathan

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