Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1997-10-07
2001-10-09
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S329000
Reexamination Certificate
active
06301259
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a switch used for receiving and transmitting data between lines in information communication systems.
2. Background of the Invention
Major types of the information communication systems, especially LAN such as Ethernet and ATM-LAN, have used a transmission line shared with all terminals. However, increase in quantity of data to be received and transmitted over LAN and increase in the number of terminals connected to LAN have increased the difficulty of obtaining sufficient transmission capacity in LAN of this type. This fact has recently encouraged the use of a LAN switch in systems so that each terminal can use the whole band of the transmission line which is available for transmission thereby solving the above-described problem.
A conventional LAN switch, however, performs data switching on the transmission line by software processing using a processor, so that it is difficult to improve processing capabilities. For example, a bottle neck in a switch device may limit the band for transmission, although, properly considering performance of the transmission line, the full bond is available for transmission.
SUMMARY OF THE INVENTION
A first aspect of the present invention is related to a switch comprising: a first unit for receiving data from a first line from which data is sent, and recognizing a second line to which data is sent on the basis of the received data; a buffer region shared with the first and second lines, for storing the data received from the first line; a register for storing information related to an address of the data stored in the buffer region and the lines from and to which the data is sent; and a second unit for reading out the data from the buffer region in accordance with the information and transmitting the data to the second line.
Preferably, according to a second aspect of the present invention, the buffer region is formed in a first memory region connected to each of the first and second units via a first bus; and the register is formed in a second memory region, different from the first memory region, connected to each of the first and second units via a second bus different from the first bus.
Preferably, according to a third aspect of the present invention, the second memory region is formed in the first and second units, respectively; and the information is transferred via a signal line connecting the first and second units in series.
Preferably, according to a fourth aspect of the present invention, the line from which data is sent consists of a plurality of the lines from which data is sent; and the register, included in the second memory region separately formed in the second unit, holds the information for each of the lines from which data is sent.
Preferably, according to a fifth aspect of the present invention, the second unit and the second line are paired up and the pair consists of a plurality of the pairs; the signal line connects a plurality of the second units in series; and one of the second units transmits the information to the signal line when receiving the information indicating that data is to be sent to the second line corresponding to another of the second units.
Preferably, according to a sixth aspect of the present invention, the second memory region further includes a table for storing destination information and transfer information associated with each other.
Preferably, according to a seventh aspect of the present invention, the data has a fixed length.
Preferably, according to an eighth aspect of the present invention, the data is divided in appropriate size to be stored in the buffer region; and the divided data are controlled in chain.
A ninth aspect of the present invention is related to a switching method comprising the steps of: (a) receiving data from a first line from which data is sent, and recognizing a second line to which data is sent on the basis of the received data; (b) transferring the data to a buffer region shared with the first and second lines; (c) storing information related to an address of the data stored in the buffer region and the lines from and to which data is sent, into a register; and (d) reading out the data from the buffer region in accordance with the information, and transmitting the data to the second line.
In accordance with the first aspect of the present invention, the switch can be structured by hardware. Further, since the buffer region is shared with the first and second lines, copy of data between the first and second units is unnecessary, realizing high-speed switching. Furthermore, stored in the register as information, both lines from and to which data is sent can be grasped.
In accordance with the second aspect of the present invention, the first and second memory regions are separately formed and connected to each of the first and second units via the first and second buses, respectively. This relieves difference in speed between the first and second memories, and bottle neck caused by difference in transfer capability between the first and second buses. Further, since the first and second buses are physically different from each other, an optimum bus in width can be adopted for each applied system.
In accordance with the third aspect of the present invention, the information related to an address of data in the buffer region or the like is transferred between units via the serial signal line, so that the number of external terminals connected to each of the first and second units can be reduced.
Further, since the first and second units, connected via the signal lines, and the second memory region are connected via respective buses, bottle neck related to a single bus can be relieved compared to the case where the first and second units share the second memory region and are connected thereto via a single bus.
In accordance with the fourth aspect of the present invention, even if there is a plurality of the lines from which data is sent, the second unit can recognize a line from which data is sent.
In accordance with the fifth aspect of the present invention, even if there is a plurality of the second lines to which data is sent, the information can be transferred to the second unit corresponding to a line to which data is sent. This brings about the same effect of the fourth aspect for the register of the second unit.
In accordance with the sixth aspect of the present invention, the register and the table are formed together in the second memory region, so that the number of external terminals connected to the first and second units can be further reduced.
In accordance with the seventh aspect of the present invention, since the data to be transmitted has a fixed length, a system for storing data into the buffer region can be optimized. This is especially applicable to the ATM-LAN.
In accordance with the eighth aspect of the present invention, even if data to be transmitted has a variable length, a system for storing data into the buffer region can be optimized. This is especially applicable to Ethernet.
In accordance with the ninth aspect of the present invention, since data is switched through the buffer region shared with the first and second lines, copy of data between the first and second units is unnecessary, realizing high-speed switching. Further, the method comprises the step of storing the information related to the lines from and to which data is sent into the register, so that the lines from and to which data is sent can be grasped.
The present invention provides a switch of high-speed performance realized not by software processing but by hardware.
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Burns Doane , Swecker, Mathis LLP
Elallam Ahmed
Kizou Hassan
Mitsubishi Denki & Kabushiki Kaisha
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