Switch and/or router unit

Details Switch and/or router unit Switch and/or router unit

2003-01-31

2004-04-27

Marcelo, Melvin (Department: 2663)

Multiplex communications

Communication techniques for information carried in plural...

Adaptive

C370S466000, C370S467000

Reexamination Certificate

active

06728260

ABSTRACT:

BACKGROUND
1. Field
The invention relates to switches, routers, and/or switch-routers.
2. Background Information
In the design of switches, routers and/or switch-routers, memory bandwidth is an issue to consider. It is common for such devices or systems to be designed employing a shared memory architecture. In such an architecture, a central resource pool is employed to store signal frames or packets received via the ports of the switch and/or router. The use of a shared memory architecture in a switch and/or router is well-known. Shared memories are described, for example, in
Computer Networks
, by Andrew S. Tanenbaum, published by Prentice-Hall, Inc., Upper Saddle River, N.J., 3d Edition, 1996. However, because each port accesses memory, this may result in a high bandwidth for the shared memory or else the shared memory may not have the capacity to handle the packets. For example, for a 24 port downlink and two port uplink switch, the bandwidth desired for memory may be on the order of 4.8 gigabits per second. Further, in a system, device, or unit that has routing capability, these frames may be forwarded from shared memory to a processing unit for processing to support different network protocols and other forms of packet management. After this processing unit has made decisions or performed such processing, the frames are typically transferred back, via shared memory, to the corresponding ports of the system or unit, for transmission. Therefore, frames are transferred in and out of shared memory multiple times, consuming memory bandwidth. A need, therefore, exists for a method or technique to address this memory bandwidth issue.
SUMMARY
Briefly, in accordance with one embodiment of the invention, a system includes: shared memory. The system includes the capability to transfer to a router processing unit a fragment of a received frame and a pointer to the fragment in shared memory.
Briefly, in accordance with another embodiment of the invention, a method of transferring a fragment of a received frame includes the following. The received frame and the byte length of a fragment of the received frame are stored in shared memory. The fragment of the received frame having the byte length indicated and a pointer to the location of the fragment in shared memory are transferred.
Briefly, in accordance with yet another embodiment of the invention, a switch-router includes at least one integrated circuit. The at least one integrated circuit includes the capability, alone or in combination with one or more other integrated circuits, to transfer to a router processing unit a fragment of a received frame and a pointer to the location of the fragment in a shared memory.


REFERENCES:
patent: 5910954 (1999-06-01), Bronstein et al.
patent: 6041328 (2000-03-01), Yu
patent: 6145016 (2000-11-01), Lai et al.

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