Swap scan testing of digital logic

Details Swap scan testing of digital logic Swap scan testing of digital logic

1987-07-16

1989-05-16

Atkinson, Charles E.

Excavating

G06F 1100, G01R 3128

Patent

active

048316237

ABSTRACT:
Apparatus and method for dynamically testing logic circuits transparent to their normal operation without placing restrictions on the logic circuit design. The apparatus is a swap scan register including an operational register for storing operational data and a test register for storing test data. The operational and test registers operate independently of each other. A swap circuit enables exchanging the operational and test register contents. According to the method disclosed after test data is stored in the test register, the operational register is interrupted and its contents swapped with the test register for one clock cycle. The test and operational registers are then swapped again to restore the original operational data to its pre-interrupt state and to provide test results in the test register.

REFERENCES:
patent: 4366393 (1982-12-01), Kasuya
patent: 4602210 (1986-07-01), Fasang et al.
patent: 4612499 (1986-09-01), Andresen et al.
patent: 4670877 (1987-06-01), Nishibe
patent: 4701916 (1987-10-01), Naven et al.
patent: 4701920 (1987-10-01), Resnick et al.

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