Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Reexamination Certificate
1999-06-17
2002-05-07
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
C361S056000, C361S058000, C361S100000
Reexamination Certificate
active
06385028
ABSTRACT:
SUMMARY OF THE INVENTION
An object of the present invention is to provide a surge preventing circuit for an insulated gate type transistor capable of accomplishing the charging operation through the gate terminal in a short time compared with the discharge time so that sufficient surge current flows in response to the activation of the insulated gate type transistor, thereby surely eliminating the parasitic bipolar operation and improving the durability against the quick surge caused by the static electricity or the like.
In order to accomplish this and other related objects, an aspect of the present invention provides a surge preventing circuit for an insulated gate type transistor with high-voltage and low-voltage terminals, one of which is connected to an electric load, and a gate terminal connected to a gate control unit. The surge preventing circuit comprises a first Zener diode having one end connected to the electric load through the one of the high-voltage and low-voltage terminals and the other end connected to the gate terminal of the insulated gate type transistor. The first Zener diode causes breakdown in response to a surge voltage applied to the one of the high-voltage and low-voltage terminals connected to the electric load. A resistor is connected between the gate terminal of the insulated gate type transistor and the gate control unit. The resistor prevents current from flowing from the one of the high-voltage and low-voltage terminals of the insulated gate type transistor to the gate control unit in an event of the breakdown of the first Zener diode. And, a second Zener diode of multiple stages is connected between the other of the high-voltage and low-voltage terminals and the gate terminal of the insulated gate type transistor. The second Zener diode clamps a gate voltage against the breakdown of the first Zener diode. A breakdown voltage of the second Zener diode is lower than a gate withstand voltage of the insulated gate type transistor.
With this arrangement, the first Zener diode causes breakdown when a surge voltage is applied to the high-voltage or low-voltage terminal of the transistor which is connected to the electric load. The resistor prevents the current from flowing from the electric load to the gate control unit via the high-voltage or low-voltage terminal of the transistor and the first Zener diode. The gate terminal is charged. When the gate voltage is increased to the threshold voltage of the transistor, the transistor is turned on. The surge current starts flowing so as to prevent the transistor from be broken.
By providing the second Zener diode between the gate terminal and the other of the high-voltage and low-voltage terminals of the insulated gate type transistor, it becomes possible to quicken the charging operation through the gate terminal and increase a reachable voltage level of the gate terminal through the charging operation. Such quick MOS transistor operation and the highly charged voltage make it possible to realize satisfactory MOS performance. Undesirable parasitic bipolar operation can be surely eliminated.
Thus, it becomes possible to improve the durability against the quick surge.
Preferably, the surge preventing circuit for an insulated gate type transistor of the present invention further comprises a third Zener diode having one end connected to an intermediate point between the gate control unit and the resistor and the other end connected to the other of the high-voltage and low-voltage terminals of the insulated gate type transistor.
According to this arrangement, the third Zener diode causes breakdown when a surge voltage is applied to the gate control unit. The surge current flows from the gate control unit to the other of the high-voltage and low-voltage terminals, thereby protecting the gate terminal of the insulated gate type transistor.
According to a preferred embodiment of the present invention, the first Zener diode is a first Zener diode group consisting of a plurality of serially connected Zener diodes having the same characteristics. And, the following equation is satisfied for the first Zener diode group.
n=BVp/Vzd
where “n” represents the total number of the Zener diodes constituting the first Zener diode group, “BVp” represents an expected breakdown voltage of the insulated gate type transistor, and “Vzd” represents a withstand voltage of one diode constituting the first Zener diode group.
According to the preferred embodiment of the present invention, the second Zener diode is a second Zener diode group consisting of a plurality of serially connected Zener diodes having the same characteristics. And, the following equation is satisfied for the second Zener diode group.
m=BVg/Vzd
where “m” represents the total number of the Zener diodes constituting the second Zener diode group, “BVg” represents the gate withstand voltage of the insulated gate type transistor, and “Vzd” represents a withstand voltage of one diode constituting the second Zener diode group.
It is further preferable that the resistor connected between the gate terminal of the insulated gate type transistor and the gate control unit has a resistance value Rg satisfying the following relationship
Rg
>
r
2
+
(
1
2
π
fC
iss
)
2
where “r” represents a sheet resistance of the gate terminal of the insulated gate type transistor, “f” represents a frequency at which a maximum spectrum intensity is obtained when an objective surge waveform is subjected to the Fourier transformation, and “Ciss” represents a gate input capacitance of the insulated gate type transistor.
It is also preferable that the resistor connected between the gate terminal of the insulated gate type transistor and the gate control unit has a resistance value larger than a quarter of a gate input impedance of the insulated gate type transistor when an objective surge is applied.
REFERENCES:
patent: 4862233 (1989-08-01), Matsushita et al.
patent: 4893158 (1990-01-01), Mihara et al.
patent: 5079608 (1992-01-01), Wodarczyck
patent: 5115369 (1992-05-01), Robb et al.
patent: 5128823 (1992-07-01), Fujimoto et al.
patent: 5162699 (1992-11-01), Fujihira
patent: 5181095 (1993-01-01), Mosher et al.
patent: 5256582 (1993-10-01), Mosher et al.
patent: 5304802 (1994-04-01), Kumagai
patent: 5365099 (1994-11-01), Phipps et al.
patent: 5397914 (1995-03-01), Suda et al.
patent: 5444595 (1995-08-01), Ishikawa et al.
patent: 5502399 (1996-03-01), Imai
patent: 5521414 (1996-05-01), Palara
patent: 5638246 (1997-06-01), Sakamoto
patent: 5691557 (1997-11-01), Watanabe
patent: 5973359 (1999-10-01), Kobayashi et al.
patent: 0060 635 (1982-09-01), None
patent: 0566 179 (1993-10-01), None
patent: 2 103 877 (1983-02-01), None
patent: 2-110976 (1990-04-01), None
Denso Corporation
Harness Dickey & Pierce PLC
Jackson Stephen W.
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