Surface planarization method for VLSI technology

Details Surface planarization method for VLSI technology Surface planarization method for VLSI technology

1986-06-03

1988-10-04

Childs, Sadie

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

156646, 156653, 427 96, 427 99, 427255, 4272553, 437228, 437231, 437235, 437245, B05D 306, B05D 512

Patent

active

047755504

ABSTRACT:
A planarization process for a double metal very large scale integration (VLSI) technology is disclosed. To compensate for an irregular surface topology encountered in a dielectric medium between the two metals, a CVD dielectric layer and a glass layer are first deposited above the first metal. Then an etch-back process is used to uniformly etch back the CVD dielectric and the glass layers at the same rate, leaving a planarized surface for subsequent deposition of a second dielectric layer and a second metal layer.

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Elkins et al., "A Planarization Process For Double Metal CMOS Using Spin-On-Glass As A Sacrificial Layer", V-MIC Conference IEEE, pp. 100-106, Jun. 9-10, 1986.

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