Active solid-state devices (e.g. – transistors – solid-state diode – With specified impurity concentration gradient – With high resistivity
Reexamination Certificate
2001-03-20
2003-09-09
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With specified impurity concentration gradient
With high resistivity
C257S458000, C257S506000, C257S594000
Reexamination Certificate
active
06617670
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to semiconductor devices and, more particularly, the invention relates to a surface PIN device and a method of manufacturing same.
2. Description of the Related Art
Planar surface antennas and other conductive structures generally rely on the use of metallization deposited upon a substrate to form the metal structures. These structures are not very accommodating to alterations or dynamic reconfiguration. Such changeable or reconfigurable structures are approximated by depositing an array of metal patches that are interconnected by switching devices or other semiconductor devices. By actively switching the devices on or off, various patches can be conductively interconnected to form various shapes of conductive structures. Such switched patches are not effective in forming antennas because the inactive patches interfere with the radiation patterns generated by the active patches. The inactive patches become passive radiators and cause parasitic anomalies in the radiation pattern.
Therefore, there is a need in the art for a method and apparatus that simulates metallization using a semiconductor-based structure.
SUMMARY OF THE INVENTION
The present invention is a surface PIN (SPIN) device and a method of fabricating such a SPIN device. The SPIN device, when activated, confines carrier injection to a small volume near the surface of the device such that the device is sufficiently conductive to simulate a planar conductor. The SPIN device comprises a P+ region and an N+ region formed in an intrinsic (I) layer. The P+ and N+ regions are separated by a lateral length of intrinsic material of length L. The length L is approximately the carrier diffusion length. When DC bias is applied across the N+ and P+ regions carriers are injected into the intrinsic region at a density exceeding 10
18
carriers per cm
3
. The intrinsic region is sufficiently thin to confine the carriers near the surface of the intrinsic region. As such, in the “on” state, the SPIN device simulates a conductive material. In the “off” state, the SPIN device is no longer conductive. Consequently, a planar array of SPIN devices can be fabricated and selectively activated to form a dynamic, reconfigurable antenna.
REFERENCES:
patent: 4751513 (1988-06-01), Daryoush et al.
patent: 5864322 (1999-01-01), Pollon et al.
patent: 6020853 (2000-02-01), Richards et al.
patent: 57 128983 (1982-08-01), None
“Optically Controlled Lateral PIN Diodes and Microwave Control Circuits”, P. J. Stabile et al., RCA Review, RCA Corp. Princeton, NJ, US, vol. 47, No. 4, Dec. 1, 1986, pp. 443-456.
“Dielectrically Isolated Lateral High Voltage P-i-N Rectifiers for Power ICs”, S. Sridhar et al., 1992 Int. Electron Devices Meeting (IEDM), New York, IEEE, US, Dec. 13, 1992, pp. 245-248.
PCT International Search Report, PCT/US01/08930, international filing date Mar. 2, 2001.
Fathy Aly E.
Perlow Stewart M.
Rosen Arye
Swain Pradyumna K.
Taylor Gordon C.
Burke William J.
Jackson Jerome
Sarnoff Corporation
LandOfFree
Surface PIN device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Surface PIN device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Surface PIN device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3073219