Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2002-01-11
2004-05-11
Zarneke, David A. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S696000
Reexamination Certificate
active
06734536
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a surface-mounting semiconductor device sealed in a resin package and having its terminals exposed on a bottom surface of the resin package.
BACKGROUND ART
FIG.
43
and
FIG. 44
show a semiconductor device Y
1
as an example of a conventional surface-mounting wire-type semiconductor device.
FIG. 43
is a sectional view of the semiconductor device Y
1
.
FIG. 44
is a perspective view of the semiconductor device Y
1
taken on the side of a bottom surface.
The semiconductor device Y
1
includes two first conductors
910
, a second conductor
920
, a semiconductor chip
930
, wires
940
and a resin package
950
. Each of the first conductors
910
includes a first terminal surface
911
. The second conductor
920
includes two second terminal surfaces
921
. The first terminal surfaces
911
and the second terminal surfaces
921
provide the semiconductor device Y
1
with electrical connection with external terminals. The semiconductor chip
930
is mounted on the second conductor
920
. The semiconductor chip
930
has a lower surface provided with a terminal (not illustrated) electrically connected with the second conductor
920
. Each wire
940
provides electrical connection between a terminal (not illustrated) formed on an upper surface of the semiconductor chip
930
and one of the first conductors
910
. The resin package
950
seals the first conductors
910
, the second conductor
920
, the semiconductor chip
930
, and the wires
940
while exposing the first terminal surfaces
910
and the second terminal surfaces
921
. The two first terminal surfaces
911
and the two second terminal surfaces
921
are in a same plane, on a bottom surface
950
a
of the resin package
950
.
According to such a semiconductor device Y
1
, in order to avoid electrical discharge between mutually opposed conductors, as shown in
FIG. 43
, the first conductors
910
and the second conductor
920
must to be spaced from each other by a distance L
6
, which must be greater than a certain minimum value. This requirement poses a problem to size reduction of the conventional semiconductor device Y
1
.
There is another problem. Specifically, if the semiconductor device Y
1
is a surface-mounting transistor for example, the number and the size of the terminals are standardized in general, in accordance with the size of the semiconductor device Y
1
. If a size (e.g. a length L
7
) of the semiconductor device Y
1
, a size (e.g. a length L
8
) of the first terminal surface
911
, and so on are provided in accordance with the standards, a size (e.g. a length L
9
) of the second conductor
920
must be relatively small according to the conventional semiconductor device Y
1
. This limits a size (e.g. a length L
10
) of the semiconductor chip
930
mountable to the second conductor
920
, leading to an occasional problem that a desired function cannot be achieved within a single semiconductor device.
FIG.
45
and
FIG. 46
show a semiconductor device Y
2
as an example of a conventional surface-mounting wireless-type semiconductor device.
FIG. 45
is a perspective view of the semiconductor device Y
2
.
FIG. 46
is a perspective view of the semiconductor device Y
2
taken from the opposite side as in FIG.
45
.
The semiconductor device Y
2
includes a first conductor
910
, a second conductor
920
, a semiconductor chip
930
, and a resin package
950
. The first conductor
910
has a bent structure including a first portion
915
, a second portion
916
, and a third portion
917
in between. The first portion
915
is bonded to an electrode (not illustrated) provided on an upper surface of the semiconductor chip
930
. The second portion
916
includes two first terminal surfaces
911
. The second conductor
920
includes two second terminal surfaces
921
. The semiconductor chip
930
is mounted on the second conductor
920
. The semiconductor chip
930
has a lower surface provided with a terminal (not illustrated) which is electrically connected with the second conductor
920
. According to the semiconductor device Y
2
, the resin package
950
seals the first conductor
910
, the second conductor
920
, the semiconductor chip
930
while exposing the first terminal surfaces
911
and the second terminal surfaces
921
. The two first terminal surfaces
911
and the two second terminal surfaces
921
are in a same plane on a bottom surface
950
a
of the resin package
950
.
According to the semiconductor device Y
2
, which includes the first conductor
910
as shown in FIG.
45
and
FIG. 46
, the third portion
917
provides electrical connection between the first terminal surfaces
911
and the electrode on the upper surface of the semiconductor chip
930
, and it is difficult to dispose this third portion along a side surface
950
b
of the resin package
950
, closely to the side surface
950
b
. Therefore, according to the semiconductor device Y
2
of a given size, size of usable semiconductor chip
930
is limited. Likewise, the size of the semiconductor device Y
2
must be increased if the semiconductor chip
930
to be mounted is larger than the second conductor
920
.
The semiconductor device Y
2
is conventionally made from a lead frame
960
as shown in FIG.
47
. The lead frame
960
includes a first region
910
A formed with a plurality of rectangular-shaped first conductor lands
910
a
each to serve as the first conductor
910
, and a second region
920
A formed with a plurality of second conductor lands
920
a
each to serve as the second conductor
920
. In the manufacture of the semiconductor device Y
2
, each first conductor land
910
a
undergoes a press-folding step, for formation of the first portion
915
, the second portion
916
and the third portion
917
. Next, a semiconductor chip
930
is mounted on each second conductor land
920
a
. Next, the first region
910
A is pivoted around a pair of bridge portions
961
and is overlapped onto the second region
920
A, into a state as shown in
FIG. 48
, in a single unit of semiconductor device formation area.
In order to reliably bond the first conductor land
910
a
with the semiconductor chip
930
after the first region
910
A is overlapped onto the second region
920
A, during the above-mentioned press-folding step performed to the first conductor land
910
a
, the first conductor land
910
a
is folded so that the first portion
915
and the third portion
917
make an acute angle slightly smaller than shown in FIG.
48
. If the first conductor land
910
a
is folded as such, during the overlapping step shown in
FIG. 48
, the first conductor land
910
a
urges the semiconductor chip
930
in a direction indicated by Arrow A.
However, the first conductor land
910
a
has a fixed base end
910
a
′. Therefore, if there is a large force acting in the direction indicated by Arrow A due to a bent of a border region between the first portion
915
and the third portion
917
, a force develops which tends to increase the acute angle between the second portion
916
and the third portion
917
. As a result, the border region between the second portion
916
and the third portion
917
is sometimes raised as indicated by Arrow B. If the border region between the second portion
916
and the third portion
917
is raised, the first terminal surface
911
of the second portion
916
is raised accordingly. It is conjectured that such a phenomenon is caused mainly by excessively high stiffness of the border region between the third portion
917
and the first portion
915
, which generates a large repelling force in the first conductor land
910
a
when a force is applied which could deform the shape of the border region.
If such a state is not corrected before the semiconductor chip
930
and the other components are sealed into the resin package
950
, the resin material invades into an underside of the first terminal surfaces
911
of the second portion
916
. Specifically, a resulting semiconductor device Y
2
has a resin package
950
having a bottom surface
950
a
whi
Merchant & Gould P.C.
Rohm & Co., Ltd.
Zarneke David A.
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