Static information storage and retrieval – Interconnection arrangements
Patent
1988-03-03
1990-01-02
Popek, Joseph A.
Static information storage and retrieval
Interconnection arrangements
365 72, 361409, 174 685, G11C 502, H05K 330
Patent
active
048917893
ABSTRACT:
A multilayer printed circuit memory board is designed and constructed so that the top and bottom layers contain repetitive integrated circuit (IC) chip component hole/pad and interconnection line patterns which are mirror images of one another. The board uses surface mounted techniques in which the integrated chip components of the memory array are mounted and soldered to both sides of the board thereby doubling the density or capacity of the memory board. The integrated circuit memory chips, mounted on the top and bottom of the board, are aligned with each other for sharing common holes or vias in which logically equivalent input signal connections are exchanged in a manner for reducing the number of holes and length of connective wiring.
REFERENCES:
patent: 4190901 (1980-02-01), Johnson et al.
patent: 4651416 (1987-03-01), DePaul
patent: 4692900 (1987-09-01), Ooami et al.
Fisher Edwin P.
Quattrini Victor L.
Bull HN Information Systems Inc.
Driscoll Faith F.
Popek Joseph A.
Solakian John S.
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