Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
2003-11-10
2004-12-14
Reichard, Dean A. (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S306300, C361S303000, C361S311000, C361S313000, C361S321100
Reexamination Certificate
active
06831824
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to surface mountable capacitors for high frequency applications, such as broadband applications.
BACKGROUND OF THE INVENTION
Broadband applications require capacitor devices that operate from low frequency. To enable such operation, the capacitor devices require a large capacitor value on the order of 10,000 pF-100,000 pF, if possible. Also important for frequency applications is a low insertion loss and low inductance. Typically, capacitor design is a compromise between the high capacitance value and low inductance and insertion loss.
The multi-layer capacitor
10
depicted in
FIG. 1
is well known in the art and includes a plurality of first and second interior electrode plates
12
,
14
within a dielectric body
16
. Such structures may be formed by printing metallizations on green ceramic layers, stacking the layers, and then cofiring the layered structure to form body
16
with interior electrode plates
12
,
14
. End conductors
20
may then be formed on opposing ends of body
16
by dipping the body
16
into a conductive paste, by printing or any other suitable method. Capacitor
10
has the benefit of being surface mountable to the circuit board traces
18
. The electrons flow from the traces
18
through the end conductors
20
into respective electrode plates
12
,
14
. A known alternative to the capacitor
10
of
FIG. 1
is the vertical multi-layer capacitor
100
shown in
FIG. 2
, which exhibits better performance properties at high frequencies than the horizontal multi-layer capacitor of FIG.
1
. Capacitor
100
includes top and bottom metallizations
102
,
104
on opposing planar surfaces
106
,
108
of dielectric body
116
and a plurality of alternating first and second interior electrode plates
112
,
114
aligned vertically with respect to the trace
118
on the printed circuit board, and substantially perpendicular to the top and bottom metallizations
102
,
104
. The body
116
with internal electrode plates
112
,
114
may be manufactured by a same or similar method as that used for capacitor
10
of FIG.
1
. The metallizations are printed on to the surfaces
106
,
108
. Unlike capacitor
10
, capacitor
100
of
FIG. 2
is not fully surface mountable, which is a disadvantage with respect to ease of assembly of the capacitor
100
onto a circuit board. Rather, capacitor
100
requires a wire bond
122
for electrically connecting the top metallization
102
to a second trace
124
on the printed circuit board. Wire bonding includes making solder connections between the wire
122
and the top metallization
102
and between the wire
122
and the trace
124
. Given the miniaturized dimensions of the components, wire bonding is an intricate process. While the vertical multi-layer capacitor
100
mounted on a trace
118
and wire bonded to a trace
124
has good performance properties at high frequencies, from a manufacturing and assembly perspective, there is a need to develop capacitors that are completely surface mountable.
SUMMARY OF THE INVENTION
The present invention provides a fully surface mountable vertical multi-layer capacitor. The capacitor has low insertion loss at high frequency and low inductance, while providing sufficiently high capacitance for use in broadband and other applications. In an exemplary embodiment of the present invention, the capacitor includes a first section comprising a ceramic dielectric material body having top and bottom opposite exterior surfaces and respective top and bottom metallization areas on those surfaces. The bottom metallization area is adapted to be surface mounted to a trace on a printed circuit board. Within the ceramic dielectric material is a plurality of alternating first and second interior electrode plates that extend between the exterior surfaces. The first electrode plates are in electrical contact with the bottom metallization area and are electrically insulated from the top metallization area. The second electrode plates are in electrical contact with the top metallization area and electrically insulated from the bottom metallization area. In this embodiment, the capacitor further includes a second section in which the body has top and bottom opposite exterior surfaces, and respective top and bottom metal surface portions. The bottom metal surface portion is adapted to be surface mounted to a trace on the printed circuit board adjacent the bottom metallization area of the first section. The top metal surface portion is electrically connected to the bottom metal surface portion by a first metal connector, and the top metal surface portion is further electrically connected to the top metallization area of the first section, thereby forming electrical contact between the trace on the printed circuit board and the top metallization area in contact with the second set of internal electrode plates.
In a first further embodiment of the present invention, the first and second sections are spaced from each other, and in a second further embodiment, the first and second sections form a single monolithic ceramic dielectric material, the sections being defined by a gap between the bottom metallization area of the first section and the bottom metal surface portion of the second section. Advantageously, in the first further embodiment, the top metallization area of the first section and the top metal surface portion of the second section are co-planar, and a metal connector provided over and therebetween is oriented substantially parallel to the co-planar top surface portion and top metallization area.
In another embodiment of the present invention, the ceramic dielectric body includes first and second spaced bottom exterior metallization areas each adapted to be mounted on the printed circuit board and a plurality of alternating and partially opposed interior electrode plates, the first set of plates being electrically connected to the first bottom metallization area and insulated from the second, and the second set of electrode plates being electrically connected to the second bottom metallization area and insulated from the first. The horizontal width of the first set of electrode plates are less than half the horizontal width of the ceramic dielectric body, and the alternating electrode plates partially oppose each other in an overlapping area in which the horizontal width is greater than the vertical length.
REFERENCES:
patent: 4661884 (1987-04-01), Seaman
patent: 4931899 (1990-06-01), Pruett
patent: 6418009 (2002-07-01), Brunette
patent: 6587327 (2003-07-01), Devoe et al.
Devoe Alan
Devoe Lambert
Ha Nguyen T.
Reichard Dean A.
Wood Herron & Evans LLP
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