Surface mount package with low coefficient of thermal expansion

Details Surface mount package with low coefficient of thermal expansion Surface mount package with low coefficient of thermal expansion

1996-07-29

1998-10-13

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

257703, 257705, H01L 23053

Patent

active

058216170

ABSTRACT:
A surface mount package for use with large area silicon device. The package uses a pressed ceramic frame and solid metal pads which are closely matched for coefficient of thermal expansion (CTE) to each other and to the silicon die. The package is specifically designed for large area die (greater than 0.0625 inches squared) and for high temperature eutectic alloy bonding. All materials of the package are CTE matched to each other and to silicon within 10%.

REFERENCES:
patent: 4680618 (1987-07-01), Kuroda et al.
patent: 4827082 (1989-05-01), Horiuchi et al.

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