Surface mount package

Equipment for production – distribution – or transformation of ene – Distribution – modification or control – Semiconductor – transistor or integrated circuit

Design Patent

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Design Patent

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D0462062

CLAIM:
The ornamental design for a surface mount package, as shown and described.

REFERENCES:
patent: 5224021 (1993-06-01), Takada et al.
patent: 5446623 (1995-08-01), Kanetake
patent: 5521429 (1996-05-01), Aono et al.
patent: 5689135 (1997-11-01), Ball
JEDEC Solid State Product Outlines, “Small Outline J-Lead” (SOJ) .300 Body Family (MS-013 Body), Issue A, Jun., 1988, MO-088, AA-AF.
JEDEC Solid State Product Outline, Low Profile Small Outline J-Lead Package (LSOJ), PRSO-J/LSOJ, Issue B, Jun., 1999, MO-199, pp. 1-5.
JEDEC Solid State Product Outlines, “Plastic Small Outline (SOJ) Package Family with .330 Inch Body Width”, Issue B, May, 1992, MO-121, pp. 1-2.

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