Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1996-02-16
1999-10-26
Kelley, Nathan K.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257742, 257773, H01L 2304
Patent
active
059733969
ABSTRACT:
A die incorporating vertical conductors, or vias, extending from active and passive devices on the active die side to the back side thereof. The vias are preferably formed in the die material matrix by introduction of a conductive material as known in the art. Such die may be employed in singulated fashion on a carrier substrate as an alternative to so-called "flip chip" die, or in vertically-stacked fashion to form a sealed multi-chip module the same size as the die from which it is formed. Certain vias of the various dice in the stack may be vertically aligned or superimposed to provide common access from each die level to a terminal such as a bond pad or C4 or other connection on the back side of the lowermost die contacting the carrier, while other stacked vias are employed for individual access from each die level to the carrier through the back side of the lowermost die. Vertical or horizontal fuse elements may be employed at some or all die levels to permit different circuit configurations on otherwise identical dice and to isolate devices at certain die levels from selected vias. Vias may be placed at any location within the periphery of a die and are preferably placed in superimposition or immediate lateral proximity to the devices on the various dice to minimize horizontal conductors whenever possible and thus employ more die surface area for device fabrication.
REFERENCES:
patent: 3761782 (1973-09-01), Youmaus
patent: 3947840 (1976-03-01), Craford et al.
patent: 4499655 (1985-02-01), Anthony
patent: 4764846 (1988-08-01), Go
patent: 4972248 (1990-11-01), Kornreich et al.
patent: 4983533 (1991-01-01), Go
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5229647 (1993-07-01), Gnadinger
patent: 5266833 (1993-11-01), Capps
patent: 5298767 (1994-03-01), Shor et al.
patent: 5378927 (1995-01-01), McAllister et al.
patent: 5386142 (1995-01-01), Kurtz et al.
patent: 5406125 (1995-04-01), Johnson et al.
patent: 5434745 (1995-07-01), Shokrgozar et al.
patent: 5455445 (1995-10-01), Kurtz et al.
patent: 5468997 (1995-11-01), Imai et al.
patent: 5481133 (1996-01-01), Hsu
patent: 5481134 (1996-01-01), Sobhani et al.
patent: 5510655 (1996-04-01), Tanielian
patent: 5528080 (1996-06-01), Goldstein
patent: 5552633 (1996-09-01), Sharna
patent: 5608264 (1997-03-01), Gual
patent: 5623160 (1997-04-01), Liberkowski
patent: 5675180 (1997-10-01), Pedersen et al.
patent: 5682062 (1997-10-01), Gavl
"Comparing the Micro SMT to Other Potential Alternatives You Find the Following"; Micro SMT, Inc.; 1993; 6 pages.
D.B. Tuckerman et al; "Laminated Memory: A New 3-Dimensional Packaging Technology for MCMs"; Proceedings of 1994 IEEE Multi-Chip Module Conference; pp. 58-63.
Kelley Nathan K.
Micro)n Technology, Inc.
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