Surface mount conductive polymer device

Details Surface mount conductive polymer device Surface mount conductive polymer device

2001-02-02

2002-04-30

Donovan, Lincoln (Department: 2832)

Electrical resistors

Resistance value responsive to a condition

Current and/or voltage

C338S313000, C338S332000, C029S612000, C029S610100

Reexamination Certificate

active

06380839

ABSTRACT:

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of conductive polymer positive temperature coefficient (PTC) devices. More specifically, it relates to conductive polymer PTC devices that are of laminar construction, and that are especially configured for surface-mount installations.
Electronic devices that include an element made from a conductive polymer have become increasingly popular, being used in a variety of applications. They have achieved widespread usage, for example, in overcurrent protection and self-regulating heater applications, in which a polymeric material having a positive temperature coefficient of resistance is employed. Examples of positive temperature coefficient (PTC) polymeric materials, and of devices incorporating such materials, are disclosed in the following U.S. patents:
U.S. Pat. No. 3,823,217—Kampe
U.S. Pat. No. 4,237,441—van Konynenburg
U.S. Pat. No. 4,238,812—Middleman et al.
U.S. Pat. No. 4,317,027—Middleman et al.
U.S. Pat. No. 4,329,726—Middleman et al.
U.S. Pat. No. 4,413,301—Middleman et al.
U.S. Pat. No. 4,426,633—Taylor
U.S. Pat. No. 4,445,026—Walker
U.S. Pat. No. 4,481,498—McTavish et al.
U.S. Pat. No. 4,545,926—Fouts, Jr. et al.
U.S. Pat. No. 4,639,818—Cherian
U.S. Pat. No. 4,647,894—Ratell
U.S. Pat. No. 4,647,896—Ratell
U.S. Pat. No. 4,685,025—Carlomagno
U.S. Pat. No. 4,774,024—Deep et al.
U.S. Pat. No. 4,689,475—Kleiner et al.
U.S. Pat. No. 4,732,701—Nishii et al.
U.S. Pat. No. 4,769,901—Nagahori
U.S. Pat. No. 4,787,135—Nagahori
U.S. Pat. No. 4,800,253—Kleiner et al.
U.S. Pat. No. 4,849,133—Yoshida et al.
U.S. Pat. No. 4,876,439—Nagahori
U.S. Pat. No. 4,884,163—Deep et al.
U.S. Pat. No. 4,907,340—Fang et al.
U.S. Pat. No. 4,951,382—Jacobs et al.
U.S. Pat. No. 4,951,384—Jacobs et al.
U.S. Pat. No. 4,955,267—Jacobs et al.
U.S. Pat. No. 4,980,541—Shafe et al.
U.S. Pat. No. 5,049,850—Evans
U.S. Pat. No. 5,140,297—Jacobs et al.
U.S. Pat. No. 5,171,774—Ueno et al.
U.S. Pat. No. 5,174,924—Yamada et al.
U.S. Pat. No. 5,178,797—Evans
U.S. Pat. No. 5,181,006—Shafe et al.
U.S. Pat. No. 5,190,697—Ohkita et al.
U.S. Pat. No. 5,195,013—Jacobs et al.
U.S. Pat. No. 5,227,946—Jacobs et al.
U.S. Pat. No. 5,241,741—Sugaya
U.S. Pat. No. 5,250,228—Baigrie et al.
U.S. Pat. No. 5,280,263—Sugaya
U.S. Pat. No. 5,358,793—Hanada et al.
One common type of construction for conductive polymer PTC devices is that which may be described as a laminated structure. Laminated conductive polymer PTC devices typically comprise a single layer of conductive polymer material sandwiched between a pair of metallic electrodes, the latter preferably being a highly-conductive, thin metal foil. See, for example, U.S. Pat. Nos. 4,426,633—Taylor; 5,089,801—Chan et al.; 4,937,551—Plasko; 4,787,135—Nagahori; 5,669,607—McGuire et al.; and 5,802,709—Hogge et al.; and International Publication Nos. WO97/06660 and WO98/12715.
In meeting a demand for higher component density on circuit boards, the trend in the industry has been toward increasing use of surface mount components as a space-saving measure. In accordance with this trend, laminated conductive polymer PTC devices have increasingly been designed and constructed as surface-mount devices (SMD's). Typically, an SMD is manufactured with a pair of opposed terminals that include a solder overcoat layer. See, e.g., U.S. Pat. No. 6,172,591, the disclosure of which is incorporated herein by reference. The device is attached to a printed circuit (PC) board by reflow soldering, whereby the solder layer on the terminals is melted when the device is brought into contact with solder-coated contact pads on the PC board. One problem with the reflow soldering process is that of so-called “tombstoning.” This effect occurs when thermal stresses experienced by the device during the reflow soldering process (due to different coefficients of thermal expansion between the foil electrodes and the layer of polymer PTC material laminated between them) cause the device to tip out of the horizontal plane. The tombstoning effect may be exacerbated when the solder melting on the terminals does not occur simultaneously, with the result that the terminal at which the solder melts more slowly is elevated with respect to the other terminal. The ultimate result of the tombstoning effect may be a solder joint that is physically and/or electrically degraded.
At present, the only practical way to address the above-described problem is by post-manufacture inspection and testing, which results in reduced yields due to rejection of PC boards with “tombstoned” devices. Furthermore, there is the possibility that some defective PC boards will escape detection, with the attendant risk that a defective board will fail after installation in a piece of electronic equipment. Accordingly, there has been a long-felt, but as yet unsatisfied need to reduce the incidence of tombstoning during the reflow soldering process.
SUMMARY OF THE INVENTION
Broadly, the present invention is a surface mount conductive polymer PTC device, comprising a layer of conductive polymer PTC material laminated between first and second metal foil electrodes to form a laminated structure, wherein a thermal stress relief area is formed in each of the electrodes. In a specific preferred embodiment, each of the thermal stress relief areas is formed as an etched-out area in one of the electrodes. The etched-out areas are equal in surface area, and they are symmetrically disposed on the two electrodes, so that the two electrodes are themselves symmetrical, and are subject to equal degrees of thermal stress relief. First and second opposed end terminals are formed on the opposed ends of the laminated structure to providing electrical connection to the first and second electrodes, respectively.
The external surfaces of the first and second electrodes are fully-metallized, except for the stress relief areas, so as to provide a large surface area for the adhesion of the upper and lower ends of the first and second terminals to the first and second electrodes, respectively. An external insulation layer applied over the metallized external electrode surfaces between the ends of the first and second terminals to provide electrical isolation between the first and second terminals, wherein the external insulation layer is flush with the upper and lower ends of the terminals. The external insulation layer also fills in the etched-out stress relief areas.
The etched-out stress relief areas in both of the electrodes provide balanced compensation for the thermal stresses induced by the unequal expansion of the polymer layer and the foil electrode layers during the reflow soldering process. Thus, the probability and the degree of thermal stress-induced tipping of the device will be reduced. Furthermore, because the tipping of the device due to thermal stresses may, in fact, contribute to the unequal melting of the solder at the terminals, the thermal stress relief provided by the etched out areas will substantially reduce, if not eliminate, the problem of tombstoning.
In another aspect, the present invention is a method of fabricating the above-described device. Broadly, such a method would comprise the steps of: (1) providing a laminated structure comprising a conductive polymer PTC layer sandwiched between first and second metal layers; (2) isolating selected areas of the first and second metal layers to form, respectively, first and second arrays of metal strips; (3) forming a plurality of thermal stress relief areas in each of the metal strips in the first and second arrays; (4) forming a first plurality of insulation areas on the exterior surface of each of the first array of metal strips and a second plurality of insulation areas on the exterior surface of each of the second array of metal strips; (5) forming a plurality of first terminals, each electrically connected to one of the metal strips in the first array, and a plurality of corresponding second terminals, each electrically connected to one of the metal strips in

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