Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Patent
1996-04-19
1998-06-16
Carroll, J.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
257 77, 257508, 257502, 257684, 257706, 257713, H01L 2334
Patent
active
057675783
ABSTRACT:
An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.
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Full English Translation of Japan Kokai 1-136,328 As Per Uspto.
Soderbarg, et al, Formation of Heat Sinks using, Bonding and Etch back Technique in Combination with Diamond Deposition, 1 Jan. 1993, page 1239, XP000432666.
Chang Mike F.
Dun Jowei
Fusser Hans-Jurgen
Ho Yueh-Se
Hshieh Fwu-Iuan
Carroll J.
Klivans Norman R.
Siliconix incorporated
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