Surface metal balancing to reduce chip carrier flexing

Details Surface metal balancing to reduce chip carrier flexing Surface metal balancing to reduce chip carrier flexing

2000-02-14

2002-12-24

Lam, Cathy (Department: 1775)

Stock material or miscellaneous articles

Structurally defined web or sheet

Discontinuous or differential coating, impregnation or bond

C174S255000, C174S260000, C257S778000, C257S779000, C257S780000

Reexamination Certificate

active

06497943

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a surface metal balancing structure for a chip carrier, and an associated method of fabrication, to reduce or eliminate thermally induced chip carrier flexing.
2. Related Art
A semiconductor chip may be mechanically and conductively coupled to a chip carrier by having conductive contacts on the chip (e.g., Controlled Collapse Chip Connection solder balls) solderably coupled to the top surface of the chip carrier. During processing steps that elevate the temperature of the chip carrier, such as during a reflow step for solderably joining the chip to the chip carrier, a spatial distribution of coefficient of thermal expansion (CTE) due to material inhomogeneities within the chip carrier may cause the chip carrier to bow (or flex) upward or downward and thus deviate from planarity. For example, there may be large copper pads on the bottom of the chip carrier to accommodate a ball grid array of solder balls for coupling the chip carrier to a circuit card, and smaller amounts of copper, such as in the form of copper circuitization and/or copper pads for joining a chip to the chip carrier on the top surface of the chip carrier. The spatial distribution of CTE, and consequent bowing or sagging of the chip carrier when the chip carrier is heated, is a result of copper imbalance between the top and bottom surfaces of the chip carrier combined with volumetric distribution within the chip carrier of materials having different magnitudes of CTE.
The preceding chip carrier flexing problem increases in severity if the chip carrier is made of compliant material, such as compliant organic material which cannot be easily handled (e.g., a material having a modulus of less than 300,000 psi). An organic chip carrier that is highly compliant may benefit from a rigid “stiffener ring” bonded to an outer perimeter of the top surface of the chip carrier in order to enhance the structural characteristics of the chip carrier. That is, the stiffener ring makes the chip carrier more mechanically stable and thus easier to handle. Unfortunately, the stiffener ring acts as a mechanical clamp on the outer perimeter of the chip carrier that constrains outer portions of the chip carrier from expanding, particularly when subjected to elevated temperature. In contrast, center portions of chip carrier at which chips are typically attached, are not constrained by the stiffener ring. Thus, expansion of the central portions, when heated, accentuates the chip carrier bowing by causing a distinct upward bulge in the central portion of the chip carrier top surface.
An adverse consequence of chip carrier bowing, particularly when a stiffener ring is used with a compliant organic chip carrier, is unreliable coupling of a chip to the chip carrier, as illustrated in
FIGS. 1 and 2
.
FIG. 1
shows a semiconductor chip
10
resting on an organic chip carrier
20
at ambient room temperature, wherein a top surface
14
of the chip carrier
20
is flat, and wherein solder balls
11
,
12
, and
13
on the semiconductor chip
10
are in conductive contact with solder bumps
24
,
25
, and
26
at the conductive pads
17
,
18
, and
19
on the top surface
14
of the chip carrier
20
, respectively. A stiffener ring
15
is bonded to the outer perimeter of the chip carrier
20
by an interfacing adhesive
16
.
FIG. 2
shows the chip carrier
20
of
FIG. 1
under temperature elevation, such as when solder from the solder bumps
24
,
25
, and
26
is reflowed around the solder balls
11
,
12
, and
13
in an attempt to conductively join the solder balls
11
,
12
, and
13
to the conductive pads
17
,
18
, and
19
, respectively. At the elevated temperature, the center the chip carrier
20
is bows (or bulges) upward in the direction
22
, such that the solder balls
11
and
13
are no longer in conductive contact with the conductive pads
17
and
19
, respectively. Thus, the chip carrier flexing impairs the ability to reliably join a chip to a chip carrier. The bowing B may exceed 2 to 3 mils during solder reflow.
A method is needed for reducing or eliminating flexing of a compliant organic chip carrier in an elevated temperature environment, and particularly when solder is reflowed around solder balls of a semiconductor chip for joining the semiconductor chip to the chip carrier.
SUMMARY OF THE INVENTION
The present invention provides an electronic structure, comprising:
a substrate including an organic dielectric material and having an internal conductive structure within and through the substrate;
a stiffener ring adhesively coupled to an outer portion of a first surface of the substrate;
a first metal structure, coupled to the first surface of the substrate, and having a surface area A
1
, and a coefficient of thermal expansion C
1
;
a second metal structure, coupled to a second surface of the substrate, and having a surface area A
2
and a coefficient of thermal expansion C
2
, wherein C
2
A
2
exceeds C
1
A
1
, and wherein the internal conductive structure conductively couples the first metal structure to the second metal structure; and
a metal pattern, adjacent to the first surface of the substrate, and having a surface area A
3
and a coefficient of thermal expansion C
3
, wherein (C
2
A
2
−C
1
A
1
−C
3
A
3
) is less than (C
2
A
2
−C
1
A
1
)in magnitude, and wherein the metal pattern is electrically insulated from any other conductive structure on or within the substrate.
The present invention provides a method for forming an electronic structure, comprising the steps of:
forming a substrate that includes an organic dielectric material and further includes an internal conductive structure within and through the substrate;
adhesively coupling a stiffener ring to an outer portion of a first surface of the substrate;
forming a first metal structure coupled to the first surface of the substrate, wherein the first metal structure has a surface area A
1
and a coefficient of thermal expansion C
1
;
forming a second metal structure coupled to a second surface of the substrate, wherein the second metal structure has a surface area A
2
and a coefficient of thermal expansion C
2
, wherein C
2
A
2
exceeds C
1
A
1
, and wherein the internal conductive structure conductively couples the first metal structure to the second metal structure; and
forming a metal pattern adjacent to the first surface of the substrate, wherein the metal pattern has a surface area A
3
and a coefficient of thermal expansion C
3
, wherein (C
2
A
2
−C
1
A
1
−C
3
A
3
) is less than (C
2
A
2
−C
1
A
1
) in magnitude, and wherein the metal pattern is electrically insulated from any other conductive structure on or within the substrate.
The present invention has the advantage of reducing or eliminating flexing of an organic chip carrier in an elevated temperature environment, particularly when solder is reflowed around solder balls of a semiconductor chip for joining the semiconductor chip to the chip carrier.
The present invention has the advantage of being implementable at little or no extra cost, inasmuch as the metal pattern may be formed concurrently with, and as part of the process of, circuitizing the chip carrier.
The present invention has the advantage of improving the structural stability of a highly compliant organic chip carrier by providing by adding mechanical rigidity where insulatively isolated metal is added to the chip carrier.
The present invention has the advantage of having bounding layers on a chip carrier wherein the coefficient of thermal expansion of the bounding layers increase than no more than a factor of about 3 as the temperature increases from just below to just above the glass transition temperature of the bounding layers.


REFERENCES:
patent: 5120573 (1992-06-01), Miyazaki et al.
patent: 5886877 (1999-03-01), Shingai et al.
patent: 5888631 (1999-03-01), Sylvester
patent: 5900312 (1999-05-01), Sylvester
patent: 6204453 (2001-03-01), Fallon et al.
patent: 6204456 (2001-03-01), Lauffer et al.
patent: 6329713

Affiliated with

Also associated with

Rating

Surface metal balancing to reduce chip carrier flexing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Surface metal balancing to reduce chip carrier flexing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Surface metal balancing to reduce chip carrier flexing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2962879