Surface field effect transistor with depressed source and/or dra

Details Surface field effect transistor with depressed source and/or dra Surface field effect transistor with depressed source and/or dra

1995-12-21

1998-06-23

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

257329, 257336, 257339, 257344, 257345, H01L 2976, H01L 2980, H01L 2994

Patent

active

RE0358274

ABSTRACT:
A surface field effect integrated transistor has the surface of the silicon in the source and drain areas lowered by 50-500 nm in respect to the surface of the silicon underneath the gate electrode by etching the silicon substrate before forming the source and drain junctions.
The transistor is sturdy and reliable because of the backing-off of the multiplication zone of the charge carriers from the gate oxide by a distance greater than several times the mean free path of hot carriers, thus markedly reducing the number of hot carriers available for injection in the gate oxide.
The modified fabrication steps are readily integrable in a normal CMOS fabrication process.

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Chakravasti et al., "Double-Difused Metal-Oxide Silicon FET," IBM Technical Disclosure Bulletin, vol. 19, No. 4, Sep. 1976, pp. 1162-1163.
Hussein I. Hanafi, Device Advantage of Dl-LDD/LDD MOSFET over DD MOSFET, pp. 13-16.
S.M. Sze, VLSI Technology "VLSI Process Integration", pp. 481-483 Second Edition.

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