Surface field effect transistor with depressed source and/or dra

Details Surface field effect transistor with depressed source and/or dra Surface field effect transistor with depressed source and/or dra

1990-05-02

1991-08-20

James, Andrew J.

357 41, 357 55, 357 56, H01L 2910, H01L 2702, H01L 2906, H01L 2978

Patent

active

050418858

ABSTRACT:
A surface field effect integrated transistor has the surface of the silicon in the source and drain areas lowered by 50-500 nm in respect to the surface of the silicon underneath the gate electrode by etching the silicon substrate before forming the source and drain junctions.
The transistor is sturdy and reliable because of the backing-off of the multiplication zone of the charge carriers from the gate oxide by a distance greater than several times the mean free path of hot carriers, thus markedly reducing the number of hot carriers available for injection in the gate oxide.
The modified fabrication steps are readily integrable in a normal CMOS fabrication process.

REFERENCES:
patent: 4167745 (1979-09-01), Ishibashi et al.
patent: 4625388 (1986-12-01), Rice
patent: 4907048 (1990-03-01), Huang
patent: 4935789 (1990-06-01), Calviello
patent: 4949136 (1990-08-01), Jain
patent: 4985744 (1991-01-01), Spratt et al.
Chakravasti et al., "Double-Diffused Metal-Oxide Silicon FET," IBM Technical Disclosure Bulletin, vol. 19, No. 4, Sep. 1976, pp. 1162-1163.

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