Surface acoustic wave-based clock and data recovery circuit

Details Surface acoustic wave-based clock and data recovery circuit Surface acoustic wave-based clock and data recovery circuit

1999-11-18

2003-11-11

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

C375S327000, C375S373000, C375S371000, C375S376000

Reexamination Certificate

active

06647079

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to communication systems and more particularly to a clock and data recovery circuit, which can be used in such systems employing a self oscillating surface acoustic wave filter.
BACKGROUND OF INVENTION
Surface Acoustic Wave (SAW) filter based clock and data recovery (CDR) circuits generate a clock for retiming data received in connection with communication networks. Systems, subsystems and associated devices rely on these types of clock circuits to function properly.
When data is lost in a phase-locked loop PLL CDR, the PLL frequency can be directly used as the system clock. The accuracy of this clock is dependent upon the reference clock used to lock the PLL. Surface acoustic wave (SAW) based clock and data recovery (CDR) circuits may also be used. A disadvantage with SAW based CDRs is the fact that when data is lost, so is the clock.
One solution to this loss of clock problem is a self oscillation SAW based CDR. However, a drawback associated with this self oscillating SAW is that operation could not be guaranteed within ITU specifications of +/−20 ppm. Delay circuits in the feedback path of the self oscillation could be adjusted in order to obtain +/−20 ppm accuracy for the frequency, but without a precise reference, such as a crystal, it would be difficult to be assured of the proper operating frequency.
A shortcoming associated with the PLL based approach is circuit complexity, power consumption and performance. PLL based circuits require a considerably higher level of circuit complexity due to the requirement that a voltage controlled oscillator (VCO) is locked to some multiple of the reference clock or data, a frequency/phase detector to generate a frequency error signal and some integrator to set the jitter transfer bandwidth. It is this complexity, not present in the SAW based solution, that gives the SAW based solutions an advantage in die size and thereby cost and power consumption. Another advantage associated with a SAW based solution is enhanced performance since it does not suffer from the 1/f noise of the PLL approach. In addition, SAW based solutions do not pick up as much board noise as the PLL solution.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a circuit is provided which is configured to recover clock and data streams from an incoming signal. The circuit comprises a multiplexer having first and second inputs, and an output. The first input is configured to receive the incoming signal, and the second input is configured to receive a reference clock signal, while the output selectively supplies one of the incoming signal and said reference clock signal. A toggling circuit, such as a flip-flop as well as a frequency multiplier circuit are further provided which are coupled to the multiplexer output. A filter circuit is coupled to the frequency multiplier circuit, and the output of the filter circuit is coupled to a second input of the toggling circuit. Moreover, the output of the filtering circuit corresponds to the recovered clock stream, and an output of said toggling circuit corresponds to the recovered data stream.


REFERENCES:
patent: 4715049 (1987-12-01), Andrews et al.
patent: 5512860 (1996-04-01), Huscroft et al.

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