Suppression of store checking

Details Suppression of store checking Suppression of store checking

2007-11-27

2007-11-27

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Architecture based instruction processing

Multiprocessor instruction

C712S203000

Reexamination Certificate

active

10283397

ABSTRACT:
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies that store checking be suppressed for the extended instruction. The extended prefix tag is an otherwise architectural opcode within an existing instruction set. The fetch logic precludes store checking for pending store events associated with the extended instruction. The translation logic is coupled to the fetch logic. The translation logic translates the extended instruction into a micro instruction sequence that sequence directs the microprocessor to exclude store checking during execution of a prescribed operation.

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