Suppression of parasitic sidewall transistors in locos structure

Details Suppression of parasitic sidewall transistors in locos structure Suppression of parasitic sidewall transistors in locos structure

1980-12-22

1983-02-15

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 148187, 156649, 357 49, 357 52, 357 91, H01L 21302, H01L 2126

Patent

active

043739652

ABSTRACT:
An improved process for eliminating parasitic sidewall transistor action associated with LOCOS isolation oxide structures. A combined oxide-nitride-oxide mask provides a large implant window and an underlying smaller oxidation window which is recessed about 11/2 microns relative to the implant window. Implantation, followed by oxidation provides a recessed isolation oxide and a buried inversion-suppressing impurity layer which spans the length of the oxide, including the "bird's beak" region.

REFERENCES:
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patent: 4008107 (1977-02-01), Hayasaka et al.
patent: 4101344 (1978-07-01), Kooi et al.
patent: 4135289 (1979-01-01), Brews et al.
patent: 4137109 (1979-06-01), Aiken et al.
patent: 4182636 (1980-01-01), Dennard et al.
Appels et al., Philips Res. Repts. 26 (Jun. 1971), 157-165.
Esch, IBM-TDB, 21 (1978), 731.
Rideout et al., IBM-TDB, 17 (1974), 949.
"LOCOS Devices", Philips Research Reports, vol. 26, No. 3, Jun. 1971, pp. 166-180.

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