Suppression of noise between phase lock loops in a selective cal

Details Suppression of noise between phase lock loops in a selective cal Suppression of noise between phase lock loops in a selective cal

1998-03-02

2000-05-16

Bost, Dwayne D.

Telecommunications

Receiver or analog modulated signal frequency converter

Local control of receiver operation

455310, H04Q 730

Patent

active

060648694

ABSTRACT:
A synthesizer (100) is used for generating a plurality of synthesized clock signals (128, 156). The synthesizer includes a clock source (102) for generating a common frequency reference signal (103), and a clock generator (104) coupled to the common frequency reference signal for generating a plurality of generated clock signals (106, 108), wherein each of the plurality of generated clock signals is offset from each other by a predetermined phase offset (189, 192). In addition, the synthesizer includes a plurality of PLLs (Phase Locked Loops) (166-168) for generating a selected one of the plurality of synthesized clock signals, wherein each of the plurality of PLLs is coupled to, and operates from, a corresponding one of the plurality of generated clock signals, and wherein the predetermined phase offset between each of the plurality of generated clock signals is known to suppress noise between the plurality of PLLs operating therefrom.

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