Suppressed clock pulse-duration modulator for direct sequence sp

Details Suppressed clock pulse-duration modulator for direct sequence sp Suppressed clock pulse-duration modulator for direct sequence sp

1985-09-30

1987-05-26

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

375 22, 380 34, 380 44, H04K 100

Patent

active

046690891

ABSTRACT:
In the disclosed digital circuit, a digital direct sequence modulation signal is converted to a suppressed clock pulse-duration modulation signal to thereby suppress the clock feature in the frequency spectra of a spread spectrum transmission system. The disclosed digital circuit includes a parallel output shift register for converting the direct sequence modulation signal to a corresponding series of four-bit digital words. The digital words supplied by the shift register are loaded into a four-bit synchronous binary counter circuit. The counter circuit counts upwardly from the value of the digital word and supplies a carry pulse to a logic circuit which, in turn, produces an output pulse, the duration of which is representative of value of the digital word supplied by the shift register. The pulse-duration modulation signal supplied by the logic circuit is modulo-2 added with a signal having one-half the clock rate of the information embedded in the direct sequence modulation signal to supply the suppressed clock pulse-duration modulation signal.

REFERENCES:
patent: 3305636 (1967-02-01), Webb
patent: 3439279 (1969-04-01), Guanella
patent: 3666889 (1972-05-01), Zegers et al.
patent: 4001728 (1977-01-01), Schneider
patent: 4112368 (1978-09-01), Ewanus et al.
patent: 4171513 (1979-10-01), Otey et al.
patent: 4467319 (1984-08-01), Uchikoshi
patent: 4502024 (1985-02-01), Nishikawa et al.
patent: 4527275 (1985-07-01), Russell
Spread Spectrum Systems, R. C. Dixon, pp. 1-12, 121-123 and 160; (Published by John Wiley & Sons, 1976).

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